Datasheet AD8079 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Dual 260 MHz Gain = +2.0 & +2.2 Buffer |
| 页数 / 页 | 12 / 10 — AD8079. +VS. OUT. –VS. 0.1µF. 10µF. *SEE TABLE I. TRIM. 200. AD8079B. TIE … |
| 修订版 | A |
| 文件格式/大小 | PDF / 357 Kb |
| 文件语言 | 英语 |
AD8079. +VS. OUT. –VS. 0.1µF. 10µF. *SEE TABLE I. TRIM. 200. AD8079B. TIE INPUT PINS. TOGETHER. TO MINIMIZE. PEAKING
该数据表的模型线
文件文字版本
AD8079 +VS IN 50
Ω
OUT RT –VS
Inverting Configuration
+VS C1 C3 0.1µF 10µF C2 C4 0.1µF 10µF –VS
Supply Bypassing Figure 30. Board Layout (Silkscreen)
+VS 50
Ω
OUT IN RT –VS *SEE TABLE I
Noninverting Configuration (G = +2)
TRIM 200
Ω
AD8079B OUT IN RT
Figure 31. Board Layout (Component Layer) Optional Gain Trim (G = +2 → +2.2)
TIE INPUT PINS +VS TOGETHER TO MINIMIZE PEAKING OUT IN RT –VS
Noninverting Configuration (G = +1) Figure 29. Inverting and Noninverting Configurations
Table I. Recommended Component Values Component –1 +1 +2/+2.2
Figure 32. Board Layout (Solder Side; Looking Through the Board) RT (Nominal) (Ω) 53.6 49.9 49.9 Small Signal BW (MHz) 220 750 260 0.1 dB Flatness (MHz) 50 100 50 –10– REV. A
Ω
OUT RT –VS
Inverting Configuration
+VS C1 C3 0.1µF 10µF C2 C4 0.1µF 10µF –VS
Supply Bypassing Figure 30. Board Layout (Silkscreen)
+VS 50
Ω
OUT IN RT –VS *SEE TABLE I
Noninverting Configuration (G = +2)
TRIM 200
Ω
AD8079B OUT IN RT
Figure 31. Board Layout (Component Layer) Optional Gain Trim (G = +2 → +2.2)
TIE INPUT PINS +VS TOGETHER TO MINIMIZE PEAKING OUT IN RT –VS
Noninverting Configuration (G = +1) Figure 29. Inverting and Noninverting Configurations
Table I. Recommended Component Values Component –1 +1 +2/+2.2
Figure 32. Board Layout (Solder Side; Looking Through the Board) RT (Nominal) (Ω) 53.6 49.9 49.9 Small Signal BW (MHz) 220 750 260 0.1 dB Flatness (MHz) 50 100 50 –10– REV. A