Datasheet LT8228 (Analog Devices) - 8

link to page 3 LT8228
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. DS1 = V1D = 48V, DS2 = BIAS = 14V, RIN1 = 1k, RIN2 = 1k, and ISHARE = INTVCC unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic
VFAULT FAULT Low Voltage IFAULT = 2mA (Fault Condition) l 0.2 0.35 V ILKGFAULT FAULT Pin Leakage Current l 1 µA VREPORT REPORT Low Voltage IREPORT = 2mA l 0.2 0.35 V ILKGREPORT REPORT Pin Leakage Current l 1 µA IPULLDRXN DRXN Pin Pull-Down Current (Boost Mode) UV1 = 0V l 100 120 µA ILKGDRXN DRXN Pin Leakage Current (Buck Mode) l 1 µA RIGND IGND Pin Resistance to GND (Sharing Enabled) l 120 200 Ω
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 12:
IB1 is defined as the average of the input bias current to the may cause permanent damage to the device. Exposure to any Absolute SNS1P and SNS1N pins. Likewise, IB2 is defined as the average of the Maximum Rating condition for an extended period may affect device input bias current to the SNS2P and SNS2N pins. The LT8228 is tested reliability and lifetime. and specified for these conditions with the voltages at the SNS1P, SNS1N,
Note 2:
An internal clamp limits the DG1 pin to a minimum of 10V above SNS2P and SNS2N pins applied through 1k input gain resistors. VRSNS1 DS1. Driving this pin to voltages beyond this clamp may damage the device. represents the voltage between the input gain resistors for the SNS1P and
Note 3:
An internal clamp limits the DG2 pin to a minimum of 10V above SNS1N pins. Likewise, VRSNS2 represents the voltage between the input DS2. Driving this pin to voltages beyond this clamp may damage the device. gain resistors for the SNS2P and SNS2N pins. VCM1 and VCM2 are the common mode voltages at the input gain resistors R
Note 4:
Negative voltages on the SW pin are limited in an application by the IN1 and RIN2. body diodes of the external NMOS device M3, or parallel Schottky diodes
Note 13:
The LT8228 is tested in a feedback loop that servos the output of when present. The SW pin is tolerant to these negative voltages in excess of the error amplifier, VC, to the internal reference voltage by tying the FB pin one diode drop below ground down to –5V, guaranteed by design. to the VC pin with all ISET pins tied to ground.
Note 5:
No external loading is allowed on this pin other than for charging
Note 14:
The LT8228 is tested in a feedback loop that servos the output the boost capacitor, C of the error amplifier VC to the internal reference voltage by tying the ISET BST. pin under test to the VC pin with the FB and other ISET pins tied to ground.
Note 6:
Do not apply a voltage or current sources to these pins. They must be connected to capacitive loads only, otherwise permanent damage may occur.
Note 15:
Current regulation error is the difference between the measured current through the sense resistor and the programmed current set by:
Note 7:
INTVCC cannot be externally driven. No external loading is allowed (1) the sense resistor R on this pin other than connecting to the ISHARE pin and the pull-up SNS, (2) the input gain resistors RIN and (3) the ISET resistor R resistor for DRXN whose value should not be less than 50k. SET. The LT8228 is tested in a feedback loop that regulates a current through R
Note 8:
The LT8228 is tested and specified under pulse load conditions SNS by tying the VC pin to the gate of a grounded N-channel MOSFET whose drain is connected to R such that T SNS. The error due to J ≅ TA. The LT8228E is 100% production tested at TA = 25°C and the SNS pin bias current across R performance is guaranteed from 0°C to 125°C. Performance at –40°C to SNS is subtracted from this specification. This specification is tested with no ripple voltage on R 125°C is assured by design, characterization and correlation with statistical SNS.
Note 16:
Current sharing error is the difference between the current process controls. The LT8228I is guaranteed over the full –40°C to 125°C through the sense resistor R operating junction temperature range. The LT8228H is guaranteed over the SNS and the average current defined by the ISHARE pin. The voltage on ISHARE represents the average ISHARE full –40°C to 150°C operating junction temperature range. currents of multiple ideal LT8228s in parallel. The LT8228 is tested in a
Note 9:
The LT8228 includes over-temperature protection that is intended feedback loop that regulates a current through R to protect the device during overload conditions. When the junction SNS by tying the VC pin to the gate of a grounded N-channel MOSFET whose drain is connected temperature exceeds 150°C, overtemperature protection is activated. to R Continuous operation above the specified maximum operating junction SNS. The current sharing loop servos the ISET1N pin voltage in boost mode or the ISET2P pin voltage in buck mode to the ISHARE pin voltage temperature may impair device reliability or permanently damage the device. of 600mV. The error due to the SNS pin bias current across RSNS is
Note 10:
Current convention. Positive current is defined as current flowing subtracted from this specification. This specification is tested with no out of the pin. ripple voltage on RSNS.
Note 11:
There is a direct conduction path from V2 to V1D through V2
Note 17:
Rise and fall times are measured using 10% and 90% levels. Delay protection MOSFET M4 and the body diode of TG MOSFET M2. In Boost times are measured using 50% levels. Rise and fall times are assured by mode, this specification limits the current into V1 from V1D through DG1. design, characterization and correlation with statistical process controls. Rev. 0 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Buck Efficiency and Operation Typical Performance Characteristics Boost Efficiency and Operation ENABLE, Supply Current and VCC SS Current, Frequency, Thresholds and Driver Protection MOSFET Controller Pin Functions Block Diagram Operation Overview Buck Mode Operation Boost Mode Operation V1 Protection MOSFET Controller Operation V2 Protection MOSFET Controller Operation Mode of Operation (DRXN) Enable and Soft-Start (Enable and SS) Paralleling Multiple Controllers (ISHARE AND IGND) BIAS Supply and VCC Regulators Strong Gate Drivers Frequency Selection, Spread Spectrum and Phase-Locked Loop (RT and SYNC) FAULT Monitoring and REPORT Feature Applications Information Introduction Programming the Switching Frequency Inductor Selection RSNS2 and RIN2 Selection for Peak Inductor Current RSET2P Selection for V2 Output Current Limit (Buck Mode) RSET2N Selection for V2 Input Current Limit (Boost Mode) RMON2 Selection for V2 Current Monitoring RSNS1 and RIN1 Selection RSET1P Selection for V1 Input Current Limit (Buck Mode) RSET1N Selection for V1 Output Current Limit (Boost Mode) RMON1 Selection for V1 Current Monitoring Output Voltage, Input Undervoltage and Output Overvoltage Programming Power MOSFET Selection and Efficiency Considerations Optional Schottky Diode (D2 and D3) Selection Top MOSFET Driver Supply (CBST, DBST) Power Path Capacitor Selection Loop Compensation Inrush Current Control Boost Output Short Protection and Timer FAULT Conditions Soft-Start REPORT Feature Paralleling Multiple LT8228s BIAS, DRVCC, INTVCC and Power Dissipation Thermal Shutdown Pin Clearance/Creepage Consideration Efficiency Considerations PC Board Layout Checklist Design Example Package Description Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Typical Application Related Parts