Datasheet LTC3894 (Analog Devices) - 9

link to page 13 link to page 13 link to page 21 LTC3894
PIN FUNCTIONS TRACK/SS (Pin 10):
Soft-Start and External Tracking Input. to ensure a graceful recovery. Connect this pin to GND The LTC3894 regulates the VFB voltage to the smaller of when the OVLO function is not used. 0.8V or the voltage on the SS pin. An internal 10μA pull-up
EXTS (Pin 15):
Source Terminal Connection for the current source is connected to this pin. A capacitor to Optional External N-Channel MOSFET. When an optional ground at this pin sets the ramp time to the final regulated external N-channel MOSFET is used to provide bias to output voltage. Alternatively, another voltage supply con- the gate driver, connect this pin to the MOSFET source nected through a resistor divider to this pin allows the terminal and connect a 0.1µF bypass capacitor next to output to track the other supply during start-up. the the pin to ensure stable operation (see Applications
PLLIN/MODE (Pin 11):
External Reference Clock Input Information section on page 21). When not in use, con- and Burst Mode Enable/Disable. When an external clock nect this pin to ground. Do not float this pin. is applied to this pin, the internal phase-locked loop will
DRVUV/EXTG (Pin 16):
Driver Undervoltage Lockout synchronize the turn-on edge of the gate drive signal with (UVLO) Select Pin and External N-Channel Gate the rising edge of the external clock. When no external Connection. This is a dual function pin. Grounding this clock is applied, this input determines the mode of opera- pin selects a UVLO threshold of 3.75V between V tion during light loading. Floating this pin selects low I IN and Q CAP. Floating or connecting it to a voltage greater than Burst Mode operation. Pulling to ground selects pulse- 400mV selects a UVLO threshold of 6V. When an external skipping mode operation. N-channel MOSFET is used for the gate driver bias, con-
PGOOD (Pin 12):
Power Good Monitor Output. This open nect its gate terminal to the pin through a 1k resistor. This drain logic output is pulled to ground when the VFB pin is selects the 6V UVLO threshold by default. 10% above its regulation point (OV) or when the PGUV pin
CAP (Pin 18):
Lower Supply Rail for Gate Driver Bias. voltage is below the PGOOD undervoltage (UV) threshold V V IN is the higher supply rail. The gate driver bias supply PGUV. There is a 100µs delay before PGOOD changes voltage (V state in response to either an OV or a UV event. IN-VCAP) is regulated to 8V when VIN is greater than 8V. A low ESR ceramic bypass capacitor of at least
FREQ (Pin 13):
Switching Frequency Setpoint Input. The 0.47μF is required from VIN to CAP pin to maintain stable switching frequency is programmed between 75kHz and voltage regulation. The capacitor value needs to increase 850 kHz by an external setpoint resistor RFREQ connected to a minimum of 2.2µF if an external N-channel MOSFET between the FREQ pin and SGND. An internal 20µA current is used for gate driver bias. To ensure stable low noise source creates a voltage across the external setpoint resis- operation, the bypass capacitor should be placed adjacent tor to set the internal oscillator frequency. Alternatively, to the VIN and CAP pins and connected using the same this pin can be driven directly by a DC voltage to set the PCB metal layer. oscillator frequency. Grounding selects a fixed operating
V
frequency of 350kHz. Floating selects a fixed operating
IN (Pin 20):
Chip Power Supply. A minimum bypass capacitor of 1µF is required from the V frequency of 535kHz. IN pin to GND. For best performance use a low ESR ceramic capacitor
OVLO (Pin 14):
Overvoltage Lockout High Impedance and place the capacitor near the VIN pin and GND pin to Input. For an adjustable VIN overvoltage protection, con- minimize the size of the high current loop. nect this pin through a resistor divider to VIN. When
GND (Exposed Pad Pin 21):
Chip Ground. The exposed the voltage on this pin is greater than the 0.8V lockout pad must be soldered to the circuit board for electrical threshold, ,the external P-channel MOSFET is turned off contact and for rated electrical and thermal performance immediately and the TRACK/SS pin is discharged to GND of the package. Rev. A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts