Datasheet LTC3835 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Low IQ Synchronous Step-Down Controller |
| 页数 / 页 | 30 / 8 — PIN FUNCTIONS (FE Package/UFD Package). CLKOUT (Pin 1/Pin 19):. PLLLPF … |
| 修订版 | F |
| 文件格式/大小 | PDF / 818 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS (FE Package/UFD Package). CLKOUT (Pin 1/Pin 19):. PLLLPF (Pin 2/Pin 20):. VIN (Pin 11/Pin 9):
该数据表的模型线
文件文字版本
link to page 13 LTC3835
PIN FUNCTIONS (FE Package/UFD Package) CLKOUT (Pin 1/Pin 19):
Open-Drain Output Clock Signal bypassing the internal LDO powered from VIN whenever available to daisychain other controller ICs for additional EXTVCC is higher than 4.7V. See EXTVCC Connection in MOSFET driver stages/phases. the Applications Information section. Do not exceed 10V
PLLLPF (Pin 2/Pin 20):
The phase-locked loop’s lowpass fil- on this pin. ter is tied to this pin when synchronizing to an external clock.
VIN (Pin 11/Pin 9):
Main Supply Pin. A bypass capacitor Alternatively, tie this pin to GND, INTVCC or leave floating to should be tied between this pin and the signal ground pin. select 250kHz, 530kHz or 400kHz switching frequency.
SW (Pin 12/Pin 10):
Switch Node Connections to Inductor.
ITH (Pin 3/Pin 1):
Error Amplifier Outputs and Switching Voltage swing at this pin is from a Schottky diode (exter- Regulator Compensation Points. The current comparator nal) voltage drop below ground to VIN. trip point increases with this control voltage.
TG (Pin 13/Pin 11):
High Current Gate Drive for Top
TRACK/SS (Pin 4/Pin 2):
External Tracking and Soft- N-Channel MOSFET. These are the outputs of floating driv- Start Input. The LTC3835 regulates the VFB voltage to ers with a voltage swing equal to INTVCC – 0.5V superim- the smaller of 0.8V or the voltage on the TRACK/SS pin. posed on the switch node voltage SW. A internal 1µA pull-up current source is connected to this
BOOST (Pin 14/Pin 12):
Bootstrapped Supply to the Top pin. A capacitor to ground at this pin sets the ramp time Side Floating Driver. A capacitor is connected between the to final regulated output voltage. Alternatively, a resistor BOOST and SW pins and a Schottky diode is tied between divider on another voltage supply connected to this pin the BOOST and INTV allows the LTC3835 output to track the other supply dur- CC pins. Voltage swing at the BOOST pin is from INTV ing startup. CC to (VIN + INTVCC).
RUN (Pin 15/Pin 13):
Digital Run Control Input for
VFB (Pin 5/Pin 3):
Receives the remotely sensed feedback Controller. Forcing this pin below 0.7V shuts down all voltage from an external resistive divider across the output. controller functions, reducing the quiescent current that
SGND (Pin 6, Exposed Pad Pin 21/Pin 4, Exposed Pad Pin
the LTC3835 draws to approximately 10µA.
21):
Small Signal Ground. Must be routed separately from
SENSE– (Pin 16/Pin 14):
The (–) Input to the Differential high current grounds to the common (–) terminals of the Current Comparator. input capacitor. The exposed pad must be soldered to the PCB for electrical contact and for rated thermal performance.
SENSE+ (Pin 17/Pin 15):
The (+) Input to the Differential Current Comparator. The I
PGND (Pin 7/Pin 5):
Driver Power Ground. Connects to TH pin voltage and controlled offsets between the SENSE– and SENSE+ pins in conjunc- the source of bottom (synchronous) N-channel MOSFET, tion with R anode of the Schottky rectifier and the (–) terminal of C SENSE set the current trip threshold. IN.
PGOOD (Pin 18/Pin 16):
Open-Drain Logic Output.
BG (Pin 8/Pin 6):
High Current Gate Drive for Bottom PGOOD is pulled to ground when the voltage on the V (Synchronous) N-Channel MOSFET. Voltage swing at this FB pin is not within ±10% of its set point. pin is from ground to INTVCC.
PLLIN/MODE (Pin 19/Pin 17):
External Synchronization
INTVCC (Pin 9/Pin 7):
Output of the Internal Linear Low Input to Phase Detector and Forced Continuous Control Dropout Regulator. The driver and control circuit are Input. When an external clock is applied to this pin, the powered from this voltage source. Must be decoupled to phase-locked loop will force the rising TG signal to be power ground with a minimum of 4.7µF tantalum or other synchronized with the rising edge of the external clock. In low ESR capacitor. this case, an R-C filter must be connected to the PLLLPF
EXTVCC (Pin 10/Pin 8):
External Power Input to an Internal pin. When not synchronizing to an external clock, this LDO Connected to INTVCC. This LDO supplies VCC power, input determines how the LTC3835 operates at light loads. Pulling this pin below 0.7V selects Burst Mode Rev. F 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS (FE Package/UFD Package) CLKOUT (Pin 1/Pin 19):
Open-Drain Output Clock Signal bypassing the internal LDO powered from VIN whenever available to daisychain other controller ICs for additional EXTVCC is higher than 4.7V. See EXTVCC Connection in MOSFET driver stages/phases. the Applications Information section. Do not exceed 10V
PLLLPF (Pin 2/Pin 20):
The phase-locked loop’s lowpass fil- on this pin. ter is tied to this pin when synchronizing to an external clock.
VIN (Pin 11/Pin 9):
Main Supply Pin. A bypass capacitor Alternatively, tie this pin to GND, INTVCC or leave floating to should be tied between this pin and the signal ground pin. select 250kHz, 530kHz or 400kHz switching frequency.
SW (Pin 12/Pin 10):
Switch Node Connections to Inductor.
ITH (Pin 3/Pin 1):
Error Amplifier Outputs and Switching Voltage swing at this pin is from a Schottky diode (exter- Regulator Compensation Points. The current comparator nal) voltage drop below ground to VIN. trip point increases with this control voltage.
TG (Pin 13/Pin 11):
High Current Gate Drive for Top
TRACK/SS (Pin 4/Pin 2):
External Tracking and Soft- N-Channel MOSFET. These are the outputs of floating driv- Start Input. The LTC3835 regulates the VFB voltage to ers with a voltage swing equal to INTVCC – 0.5V superim- the smaller of 0.8V or the voltage on the TRACK/SS pin. posed on the switch node voltage SW. A internal 1µA pull-up current source is connected to this
BOOST (Pin 14/Pin 12):
Bootstrapped Supply to the Top pin. A capacitor to ground at this pin sets the ramp time Side Floating Driver. A capacitor is connected between the to final regulated output voltage. Alternatively, a resistor BOOST and SW pins and a Schottky diode is tied between divider on another voltage supply connected to this pin the BOOST and INTV allows the LTC3835 output to track the other supply dur- CC pins. Voltage swing at the BOOST pin is from INTV ing startup. CC to (VIN + INTVCC).
RUN (Pin 15/Pin 13):
Digital Run Control Input for
VFB (Pin 5/Pin 3):
Receives the remotely sensed feedback Controller. Forcing this pin below 0.7V shuts down all voltage from an external resistive divider across the output. controller functions, reducing the quiescent current that
SGND (Pin 6, Exposed Pad Pin 21/Pin 4, Exposed Pad Pin
the LTC3835 draws to approximately 10µA.
21):
Small Signal Ground. Must be routed separately from
SENSE– (Pin 16/Pin 14):
The (–) Input to the Differential high current grounds to the common (–) terminals of the Current Comparator. input capacitor. The exposed pad must be soldered to the PCB for electrical contact and for rated thermal performance.
SENSE+ (Pin 17/Pin 15):
The (+) Input to the Differential Current Comparator. The I
PGND (Pin 7/Pin 5):
Driver Power Ground. Connects to TH pin voltage and controlled offsets between the SENSE– and SENSE+ pins in conjunc- the source of bottom (synchronous) N-channel MOSFET, tion with R anode of the Schottky rectifier and the (–) terminal of C SENSE set the current trip threshold. IN.
PGOOD (Pin 18/Pin 16):
Open-Drain Logic Output.
BG (Pin 8/Pin 6):
High Current Gate Drive for Bottom PGOOD is pulled to ground when the voltage on the V (Synchronous) N-Channel MOSFET. Voltage swing at this FB pin is not within ±10% of its set point. pin is from ground to INTVCC.
PLLIN/MODE (Pin 19/Pin 17):
External Synchronization
INTVCC (Pin 9/Pin 7):
Output of the Internal Linear Low Input to Phase Detector and Forced Continuous Control Dropout Regulator. The driver and control circuit are Input. When an external clock is applied to this pin, the powered from this voltage source. Must be decoupled to phase-locked loop will force the rising TG signal to be power ground with a minimum of 4.7µF tantalum or other synchronized with the rising edge of the external clock. In low ESR capacitor. this case, an R-C filter must be connected to the PLLLPF
EXTVCC (Pin 10/Pin 8):
External Power Input to an Internal pin. When not synchronizing to an external clock, this LDO Connected to INTVCC. This LDO supplies VCC power, input determines how the LTC3835 operates at light loads. Pulling this pin below 0.7V selects Burst Mode Rev. F 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts