Datasheet SLG46826 (Dialog Semiconductor) - 6
| 制造商 | Dialog Semiconductor |
| 描述 | GreenPAK Programmable Mixed-signal Matrix with In System Programmability |
| 页数 / 页 | 188 / 6 — SLG46826. Tables. Datasheet. Revision 3.11. 10-Mar-2020 |
| 文件格式/大小 | PDF / 3.1 Mb |
| 文件语言 | 英语 |
SLG46826. Tables. Datasheet. Revision 3.11. 10-Mar-2020
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SLG46826
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability
Tables
Table 1: Functional Pin Description. 9 Table 2: Pin Type Definitions . 12 Table 3: Absolute Maximum Ratings . 13 Table 4: Electrostatic Discharge Ratings . 13 Table 5: Recommended Operating Conditions . 13 Table 6: EС at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted . 14 Table 7: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted . 19 Table 8: I2C Pins Timing Characteristics at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted. 20 Table 9: Typical Current Estimated for Each Macrocell at T = -40 °C to +85 °C . 21 Table 10: Typical Delay Estimated for Each Macrocell at T = 25 °C . 23 Table 11: Programmable Delay Expected Delays and Widths (Typical) at T = 25 °C . 25 Table 12: Typical Filter Rejection Pulse Width at T = 25 °C . 25 Table 13: Typical Counter/Delay Offset Measurements at T = 25 °C . 25 Table 14: Oscillators Frequency Limits, VDD = 2.3 V to 5.5 V. 26 Table 15: Oscillators Power-On Delay at T = 25 °C, OSC Power Mode: "Auto Power-On". 26 Table 16: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted . 27 Table 17: TS Output vs Temperature (Output Range 1) . 31 Table 18: TS Output vs Temperature (Output Range 2) . 31 Table 19: TS Output Error (Output Range 1) . 31 Table 20: TS Output Error (Output Range 2) . 32 Table 21: Matrix Input Table. 43 Table 22: Matrix Output Table. 44 Table 23: Connection Matrix Virtual Inputs . 48 Table 24: 2-bit LUT0 Truth Table . 51 Table 25: 2-bit LUT1 Truth Table . 51 Table 26: 2-bit LUT2 Truth Table . 51 Table 27: 2-bit LUT Standard Digital Functions . 51 Table 28: 2-bit LUT1 Truth Table . 54 Table 29: 2-bit LUT Standard Digital Functions . 54 Table 30: 3-bit LUT0 Truth Table . 58 Table 31: 3-bit LUT1 Truth Table . 58 Table 32: 3-bit LUT2 Truth Table . 58 Table 33: 3-bit LUT3 Truth Table . 58 Table 34: 3-bit LUT4 Truth Table . 58 Table 35: 3-bit LUT5 Truth Table . 58 Table 36: 3-bit LUT Standard Digital Functions . 59 Table 37: 3-bit LUT6 Truth Table . 64 Table 38: 3-bit LUT7 Truth Table . 74 Table 39: 3-bit LUT8 Truth Table . 74 Table 40: 3-bit LUT9 Truth Table . 74 Table 41: 3-bit LUT10 Truth Table . 74 Table 42: 3-bit LUT11 Truth Table . 74 Table 43: 3-bit LUT12 Truth Table . 74 Table 44: 3-bit LUT13 Truth Table . 74 Table 45: 4-bit LUT0 Truth Table . 85 Table 46: 4-bit LUT Standard Digital Functions . 85 Table 47: Vref Selection Table . 101 Table 48: Oscillator Operation Mode Configuration Settings . 105 Table 49: Oscillator Output Duty Cycle . 114 Table 50: RPR Format . 123 Table 51: RPR Bit Function Description. 123 Table 52: NPR Format . 124 Table 53: NPR Bit Function Description. 124 Table 54: Read/Write Register Protection Options . 124 Table 55: Erase Register Bit format . 129 Table 56: Erase Register Bit Function Description . 129 Table 57: Write/Erase Protect Register Format . 130 Table 58: Write/Erase Protect Register Bit Function Description . 130 Table 59: Register Map . 134
Datasheet Revision 3.11 10-Mar-2020
6 of 188 © 2020 Dialog Semiconductor CFR0011-120-00 Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN- 20L 2.2 Pin Configuration - TSSOP-20L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 OSC Characteristics 3.6.1 OSC Specifications 3.6.2 OSC Power-On Delay 3.7 ACMP Specifications 3.8 Analog Temperature Sensor Characteristics 4 User Programmability 5 IO Pins 5.1 IO Pins 5.2 GPIO Pins 5.3 GPO Pins 5.4 GPI Pins 5.5 Pull-Up/Down Resistors 5.6 Fast Pull-up/down during Power-up 5.7 I2C Mode IO Structure (VDD or VDD2) 5.7.1 I2C Mode Structure (for SCL and SDA) 5.8 Matrix OE IO Structure (VDD or VDD2) 5.8.1 Matrix OE IO Structure (for IOs 1, 4, 5 with VDD, and IOs 8, 9, 10, 11, 12, 13, 14 with VDD2) 5.9 Register OE IO Structure (VDD or VDD2) 5.9.1 Register OE IO Structure (for IOs 0, 2, 3 with VDD) 5.10 Register OE IO Structure (VDD or VDD2) 5.10.1 Register OE IO Structure (for IO 6 with VDD, and IO 7 with VDD2) 5.11 IO Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.4.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/LATCH with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 CNT/DLY/FSM Timing Diagrams 8.2.1 Delay Mode CNT/DLY0 to CNT/DLY7 8.2.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY7 8.2.3 One-Shot Mode CNT/DLY0 to CNT/DLY7 8.2.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY7 8.2.5 Edge Detection Mode CNT/DLY1 to CNT/DLY7 8.2.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY7 8.2.7 CNT/FSM Mode CNT/DLY0 8.2.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.3 4-Bit LUT or DFF/LATCH with 16-Bit Counter/Delay Macrocell 8.3.1 4-Bit LUT or 16-Bit CNT/DLY Block Diagram 8.3.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 ACMP0H Block Diagram 9.2 ACMP1H Block Diagram 9.3 ACMP2L Block Diagram 9.4 ACMP3L Block Diagram 9.5 ACMP Typical Performance 10 Programmable Delay/Edge Detector 10.1 Programmable Delay Timing Diagram - Edge Detector Output 11 Additional Logic Function. Deglitch Filter 12 Voltage Reference 12.1 Voltage Reference Overview 12.2 Vref Selection Table 12.3 Vref Block Diagram 12.4 VREF Load Regulation 13 Clocking 13.1 Oscillator general description 13.2 Oscillator0 (2.048 kHz) 13.3 Oscillator1 (2.048 MHz) 13.4 Oscillator2 (25 MHz) 13.5 CNT/DLY Clock Scheme 13.6 External Clocking 13.6.1 IO0 Source for Oscillator0 (2.048 kHz) 13.6.2 IO10 Source for Oscillator1 (2.048 MHz) 13.6.3 IO8 Source for Oscillator2 (25 MHz) 13.7 Oscillators Power-On Delay 13.8 Oscillators Accuracy 14 Power-On Reset 14.1 General Operation 14.2 POR Sequence 14.3 Macrocells Output States During POR Sequence 14.3.1 Initialization 14.3.2 Power-Down 15 I2C Serial Communications Macrocell 15.1 I2C Serial Communications Macrocell Overview 15.2 I2C Serial Communications Device Addressing 15.3 I2C Serial General Timing 15.4 I2C Serial Communications Commands 15.4.1 Byte Write Command 15.4.2 Sequential Write Command 15.4.3 Current Address Read Command 15.4.4 Random Read Command 15.4.5 Sequential Read Command 15.4.6 I2C Serial Reset Command 15.5 Chip Configuration Data Protection 15.6 I2C Serial Command Register Map 15.7 I2C Additional Options 15.7.1 Reading Counter Data via I2C 15.7.2 I2C Expander 15.7.3 I2C Byte Write Bit Masking 16 Non-Volatile Memory 16.1 Serial NVM Write Operations 16.2 Serial NVM Read Operations 16.3 Serial NVM Erase Operations 16.4 Acknowledge Polling 16.5 Low power standby mode 16.6 Emulated EEPROM Write Protection 17 Analog Temperature Sensor 18 Register Definitions 18.1 Register Map 19 Package Top Marking System Definition 19.1 STQFN 20L 2 mm x 3 mm 0.4P FCD Package 19.2 TSSOP-20 20 Package Information 20.1 Package outlines for STQFN 20L 2 mm x 3 mm 0.4P FCD 20.2 Package outlines for TSSOP 20L 173 MIL Green 20.3 STQFN and TSSOP Handling 20.4 Soldering Information 21 Ordering Information 21.1 Tape and Reel Specifications 21.2 Carrier Tape Drawing and Dimensions 21.3 STQFN-20L 21.4 TSSOP-20L 22 Layout Guidelines 22.1 STQFN 20L 2 mm x 3 mm 0.4P FCD Package 22.2 TSSOP-20 Glossary Revision History
SLG46826
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability
Tables
Table 1: Functional Pin Description. 9 Table 2: Pin Type Definitions . 12 Table 3: Absolute Maximum Ratings . 13 Table 4: Electrostatic Discharge Ratings . 13 Table 5: Recommended Operating Conditions . 13 Table 6: EС at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted . 14 Table 7: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted . 19 Table 8: I2C Pins Timing Characteristics at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted. 20 Table 9: Typical Current Estimated for Each Macrocell at T = -40 °C to +85 °C . 21 Table 10: Typical Delay Estimated for Each Macrocell at T = 25 °C . 23 Table 11: Programmable Delay Expected Delays and Widths (Typical) at T = 25 °C . 25 Table 12: Typical Filter Rejection Pulse Width at T = 25 °C . 25 Table 13: Typical Counter/Delay Offset Measurements at T = 25 °C . 25 Table 14: Oscillators Frequency Limits, VDD = 2.3 V to 5.5 V. 26 Table 15: Oscillators Power-On Delay at T = 25 °C, OSC Power Mode: "Auto Power-On". 26 Table 16: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted . 27 Table 17: TS Output vs Temperature (Output Range 1) . 31 Table 18: TS Output vs Temperature (Output Range 2) . 31 Table 19: TS Output Error (Output Range 1) . 31 Table 20: TS Output Error (Output Range 2) . 32 Table 21: Matrix Input Table. 43 Table 22: Matrix Output Table. 44 Table 23: Connection Matrix Virtual Inputs . 48 Table 24: 2-bit LUT0 Truth Table . 51 Table 25: 2-bit LUT1 Truth Table . 51 Table 26: 2-bit LUT2 Truth Table . 51 Table 27: 2-bit LUT Standard Digital Functions . 51 Table 28: 2-bit LUT1 Truth Table . 54 Table 29: 2-bit LUT Standard Digital Functions . 54 Table 30: 3-bit LUT0 Truth Table . 58 Table 31: 3-bit LUT1 Truth Table . 58 Table 32: 3-bit LUT2 Truth Table . 58 Table 33: 3-bit LUT3 Truth Table . 58 Table 34: 3-bit LUT4 Truth Table . 58 Table 35: 3-bit LUT5 Truth Table . 58 Table 36: 3-bit LUT Standard Digital Functions . 59 Table 37: 3-bit LUT6 Truth Table . 64 Table 38: 3-bit LUT7 Truth Table . 74 Table 39: 3-bit LUT8 Truth Table . 74 Table 40: 3-bit LUT9 Truth Table . 74 Table 41: 3-bit LUT10 Truth Table . 74 Table 42: 3-bit LUT11 Truth Table . 74 Table 43: 3-bit LUT12 Truth Table . 74 Table 44: 3-bit LUT13 Truth Table . 74 Table 45: 4-bit LUT0 Truth Table . 85 Table 46: 4-bit LUT Standard Digital Functions . 85 Table 47: Vref Selection Table . 101 Table 48: Oscillator Operation Mode Configuration Settings . 105 Table 49: Oscillator Output Duty Cycle . 114 Table 50: RPR Format . 123 Table 51: RPR Bit Function Description. 123 Table 52: NPR Format . 124 Table 53: NPR Bit Function Description. 124 Table 54: Read/Write Register Protection Options . 124 Table 55: Erase Register Bit format . 129 Table 56: Erase Register Bit Function Description . 129 Table 57: Write/Erase Protect Register Format . 130 Table 58: Write/Erase Protect Register Bit Function Description . 130 Table 59: Register Map . 134
Datasheet Revision 3.11 10-Mar-2020
6 of 188 © 2020 Dialog Semiconductor CFR0011-120-00 Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN- 20L 2.2 Pin Configuration - TSSOP-20L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 OSC Characteristics 3.6.1 OSC Specifications 3.6.2 OSC Power-On Delay 3.7 ACMP Specifications 3.8 Analog Temperature Sensor Characteristics 4 User Programmability 5 IO Pins 5.1 IO Pins 5.2 GPIO Pins 5.3 GPO Pins 5.4 GPI Pins 5.5 Pull-Up/Down Resistors 5.6 Fast Pull-up/down during Power-up 5.7 I2C Mode IO Structure (VDD or VDD2) 5.7.1 I2C Mode Structure (for SCL and SDA) 5.8 Matrix OE IO Structure (VDD or VDD2) 5.8.1 Matrix OE IO Structure (for IOs 1, 4, 5 with VDD, and IOs 8, 9, 10, 11, 12, 13, 14 with VDD2) 5.9 Register OE IO Structure (VDD or VDD2) 5.9.1 Register OE IO Structure (for IOs 0, 2, 3 with VDD) 5.10 Register OE IO Structure (VDD or VDD2) 5.10.1 Register OE IO Structure (for IO 6 with VDD, and IO 7 with VDD2) 5.11 IO Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.4.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/LATCH with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 CNT/DLY/FSM Timing Diagrams 8.2.1 Delay Mode CNT/DLY0 to CNT/DLY7 8.2.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY7 8.2.3 One-Shot Mode CNT/DLY0 to CNT/DLY7 8.2.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY7 8.2.5 Edge Detection Mode CNT/DLY1 to CNT/DLY7 8.2.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY7 8.2.7 CNT/FSM Mode CNT/DLY0 8.2.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.3 4-Bit LUT or DFF/LATCH with 16-Bit Counter/Delay Macrocell 8.3.1 4-Bit LUT or 16-Bit CNT/DLY Block Diagram 8.3.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 ACMP0H Block Diagram 9.2 ACMP1H Block Diagram 9.3 ACMP2L Block Diagram 9.4 ACMP3L Block Diagram 9.5 ACMP Typical Performance 10 Programmable Delay/Edge Detector 10.1 Programmable Delay Timing Diagram - Edge Detector Output 11 Additional Logic Function. Deglitch Filter 12 Voltage Reference 12.1 Voltage Reference Overview 12.2 Vref Selection Table 12.3 Vref Block Diagram 12.4 VREF Load Regulation 13 Clocking 13.1 Oscillator general description 13.2 Oscillator0 (2.048 kHz) 13.3 Oscillator1 (2.048 MHz) 13.4 Oscillator2 (25 MHz) 13.5 CNT/DLY Clock Scheme 13.6 External Clocking 13.6.1 IO0 Source for Oscillator0 (2.048 kHz) 13.6.2 IO10 Source for Oscillator1 (2.048 MHz) 13.6.3 IO8 Source for Oscillator2 (25 MHz) 13.7 Oscillators Power-On Delay 13.8 Oscillators Accuracy 14 Power-On Reset 14.1 General Operation 14.2 POR Sequence 14.3 Macrocells Output States During POR Sequence 14.3.1 Initialization 14.3.2 Power-Down 15 I2C Serial Communications Macrocell 15.1 I2C Serial Communications Macrocell Overview 15.2 I2C Serial Communications Device Addressing 15.3 I2C Serial General Timing 15.4 I2C Serial Communications Commands 15.4.1 Byte Write Command 15.4.2 Sequential Write Command 15.4.3 Current Address Read Command 15.4.4 Random Read Command 15.4.5 Sequential Read Command 15.4.6 I2C Serial Reset Command 15.5 Chip Configuration Data Protection 15.6 I2C Serial Command Register Map 15.7 I2C Additional Options 15.7.1 Reading Counter Data via I2C 15.7.2 I2C Expander 15.7.3 I2C Byte Write Bit Masking 16 Non-Volatile Memory 16.1 Serial NVM Write Operations 16.2 Serial NVM Read Operations 16.3 Serial NVM Erase Operations 16.4 Acknowledge Polling 16.5 Low power standby mode 16.6 Emulated EEPROM Write Protection 17 Analog Temperature Sensor 18 Register Definitions 18.1 Register Map 19 Package Top Marking System Definition 19.1 STQFN 20L 2 mm x 3 mm 0.4P FCD Package 19.2 TSSOP-20 20 Package Information 20.1 Package outlines for STQFN 20L 2 mm x 3 mm 0.4P FCD 20.2 Package outlines for TSSOP 20L 173 MIL Green 20.3 STQFN and TSSOP Handling 20.4 Soldering Information 21 Ordering Information 21.1 Tape and Reel Specifications 21.2 Carrier Tape Drawing and Dimensions 21.3 STQFN-20L 21.4 TSSOP-20L 22 Layout Guidelines 22.1 STQFN 20L 2 mm x 3 mm 0.4P FCD Package 22.2 TSSOP-20 Glossary Revision History