Datasheet VCNL3030X01 (Vishay) - 4
| 制造商 | Vishay |
| 描述 | Fully Integrated Proximity Sensor With Infrared Emitter, I2C Interface, and Interrupt Function |
| 页数 / 页 | 16 / 4 — VCNL3030X01. I2C BUS TIMING CHARACTERISTICS. STANDARD MODE. FAST MODE. … |
| 文件格式/大小 | PDF / 271 Kb |
| 文件语言 | 英语 |
VCNL3030X01. I2C BUS TIMING CHARACTERISTICS. STANDARD MODE. FAST MODE. PARAMETER. SYMBOL. UNIT. MIN. MAX
该数据表的模型线
文件文字版本
VCNL3030X01
www.vishay.com Vishay Semiconductors
I2C BUS TIMING CHARACTERISTICS
(Tamb = 25 °C, unless otherwise specified)
STANDARD MODE FAST MODE PARAMETER SYMBOL UNIT MIN. MAX. MIN. MAX.
Clock frequency f(I2CCLK) 10 100 10 400 kHz Bus free time between start and stop condition t(BUF) 4.7 - 1.3 - μs Hold time after (repeated) start condition; t after this period, the first clock is generated (HDSTA) 4.0 - 0.6 - μs Repeated start condition setup time t(SUSTA) 4.7 - 0.6 - μs Stop condition setup time t(SUSTO) 4.0 - 0.6 - μs Data hold time t(HDDAT) - 3450 - 900 ns Data setup time t(SUDAT) 250 - 100 - ns I2C clock (SCK) low period t(LOW) 4.7 - 1.3 - μs I2C clock (SCK) high period t(HIGH) 4.0 - 0.6 - μs Clock / data fall time tf - 300 - 300 ns Clock / data rise time tr - 1000 - 300 ns t(LOW) tr tf VIH I2C bus CLOCK VIL (SCLK) t(HDSTA) t(HIGH) t(SUSTA) t(SUSTO) t(BUF) t(HDDAT) t(SUDAT) I2C bus VIH DATA (SDAT) VIL { { { { P S S P Stop condition Start condition Start Stop t(LOSEXT) SCLKACK SDAACK t(LOWMEXT) t(LOWMEXT) t(LOWMEXT) I2C bus CLOCK (SCLK) I2C bus DATA (SDAT) Fig. 2 - I2C Bus Timing Diagram Rev. 1.0, 12-Aug-2020
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Document Number: 84960 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Semiconductors
I2C BUS TIMING CHARACTERISTICS
(Tamb = 25 °C, unless otherwise specified)
STANDARD MODE FAST MODE PARAMETER SYMBOL UNIT MIN. MAX. MIN. MAX.
Clock frequency f(I2CCLK) 10 100 10 400 kHz Bus free time between start and stop condition t(BUF) 4.7 - 1.3 - μs Hold time after (repeated) start condition; t after this period, the first clock is generated (HDSTA) 4.0 - 0.6 - μs Repeated start condition setup time t(SUSTA) 4.7 - 0.6 - μs Stop condition setup time t(SUSTO) 4.0 - 0.6 - μs Data hold time t(HDDAT) - 3450 - 900 ns Data setup time t(SUDAT) 250 - 100 - ns I2C clock (SCK) low period t(LOW) 4.7 - 1.3 - μs I2C clock (SCK) high period t(HIGH) 4.0 - 0.6 - μs Clock / data fall time tf - 300 - 300 ns Clock / data rise time tr - 1000 - 300 ns t(LOW) tr tf VIH I2C bus CLOCK VIL (SCLK) t(HDSTA) t(HIGH) t(SUSTA) t(SUSTO) t(BUF) t(HDDAT) t(SUDAT) I2C bus VIH DATA (SDAT) VIL { { { { P S S P Stop condition Start condition Start Stop t(LOSEXT) SCLKACK SDAACK t(LOWMEXT) t(LOWMEXT) t(LOWMEXT) I2C bus CLOCK (SCLK) I2C bus DATA (SDAT) Fig. 2 - I2C Bus Timing Diagram Rev. 1.0, 12-Aug-2020
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Document Number: 84960 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000