Datasheet MC1488 (ON Semiconductor) - 7
| 制造商 | ON Semiconductor |
| 描述 | Quad Line EIA-232D Driver |
| 页数 / 页 | 14 / 7 — MC1488. Figure 16. DTL/TTL−to−MOS Translator. Figure 17. Logic Translator … |
| 修订版 | 9 |
| 文件格式/大小 | PDF / 343 Kb |
| 文件语言 | 英语 |
MC1488. Figure 16. DTL/TTL−to−MOS Translator. Figure 17. Logic Translator Applications. http://onsemi.com
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MC1488
2. Power Supply Range − as can be seen from the MC1488 will drive the output to within 2.0 V of the positive schematic drawing of the drivers, the positive and negative or negative supplies as long as the current output limits are not driving elements of the device are essentially independent exceeded. The combination of the current limiting and supply and do not require matching power supplies. In fact, the voltage features allow a wide combination of possible outputs positive supply can vary from a minimum 7.0 V (required for within the same quad package. Thus if only a portion of the driving the negative pulldown section) to the maximum four drivers are used for driving EIA−232D lines, the specified 15 V. The negative supply can vary from remainder could be used for DTL to MOS or even DTL to approximately − 2.5 V to the minimum specified − 15 V. The DTL translation. Figure 17 shows one such combination. 12 V 2 3 DTL RTL Output Input -0.7 V to +3.7 V 1/4 MC1488 DTL 4 6 3.0 V DTL NAND DTL Output MOS Output TTL Gate -0.7 V to +5.7 V (with VSS = GND) Input 1.0 k Input 5 MC1488 10 k 9 DTL 8 5.0 V HTL Output HTL -0.7 V to 10 V Input 10 -12 V -12 V 12 DTL 11
Figure 16. DTL/TTL−to−MOS Translator
MOS Output MMOS -10 V to 0 V Input 1.0 k 13 10 k 1 7 14 -12 V 12 V
Figure 17. Logic Translator Applications http://onsemi.com 7
MC1488
2. Power Supply Range − as can be seen from the MC1488 will drive the output to within 2.0 V of the positive schematic drawing of the drivers, the positive and negative or negative supplies as long as the current output limits are not driving elements of the device are essentially independent exceeded. The combination of the current limiting and supply and do not require matching power supplies. In fact, the voltage features allow a wide combination of possible outputs positive supply can vary from a minimum 7.0 V (required for within the same quad package. Thus if only a portion of the driving the negative pulldown section) to the maximum four drivers are used for driving EIA−232D lines, the specified 15 V. The negative supply can vary from remainder could be used for DTL to MOS or even DTL to approximately − 2.5 V to the minimum specified − 15 V. The DTL translation. Figure 17 shows one such combination. 12 V 2 3 DTL RTL Output Input -0.7 V to +3.7 V 1/4 MC1488 DTL 4 6 3.0 V DTL NAND DTL Output MOS Output TTL Gate -0.7 V to +5.7 V (with VSS = GND) Input 1.0 k Input 5 MC1488 10 k 9 DTL 8 5.0 V HTL Output HTL -0.7 V to 10 V Input 10 -12 V -12 V 12 DTL 11
Figure 16. DTL/TTL−to−MOS Translator
MOS Output MMOS -10 V to 0 V Input 1.0 k 13 10 k 1 7 14 -12 V 12 V
Figure 17. Logic Translator Applications http://onsemi.com 7