Datasheet 1ED38x0Mc12M (1ED-X3 Digital) (Infineon) - 7

制造商Infineon
描述EiceDRIVER 1ED38x0Mc12M Enhanced. Single-channel isolated gate driver IC with I2C configurability for DESAT, Soft-off, UVLO, Miller clamp and two-level turn-off
页数 / 页47 / 7 — EiceDRIVER™ 1ED38x0Mc12M Enhanced. Datasheet. 3 Pin configuration and …
修订版02_00
文件格式/大小PDF / 722 Kb
文件语言英语

EiceDRIVER™ 1ED38x0Mc12M Enhanced. Datasheet. 3 Pin configuration and functionality. Pin configuration and functionality

EiceDRIVER™ 1ED38x0Mc12M Enhanced Datasheet 3 Pin configuration and functionality Pin configuration and functionality

该数据表的模型线

文件文字版本

EiceDRIVER™ 1ED38x0Mc12M Enhanced Datasheet 3 Pin configuration and functionality 3 Pin configuration and functionality
The pin assignment at the gate driver IC generally differentiates between the input side and the output side.
Table 1 General pin assignment Pins Designation
1 to 8 input side, input logic signal side, or low voltage side 9 to 16 output side, driver power side, or high voltage side For simplicity reasons the driver is described as an IGBT driver. For use with MOSFETs and other power switches simply replace any mentioning of collector and emitter with their corresponding pin names.
3.1 Pin configuration Table 2 Pin configuration table abbreviations Abbreviation Description
Pin type
PWR
Power supply and gate current output pins
I/O
Digital input and output pin
I
Digital input pin
GND
Ground reference pin
AI
Analog input pin Buffer type
OD
Open drain output
CMOS
CMOS compatible input threshold levels
PP
Push/pull output buffer
analog
Analog input buffer
special
Special output/input function, see individual description Pull device
PD
Pull-down resistor
CS
Current source
Table 3 Pin configuration Pin Pin name Pin type Buffer type Pull Function no. device
1 GND1 GND – – Ground input side 2 VCC1 PWR – – Positive power supply input side 3 SCL I CMOS – Clock input of serial I2C bus 4 SDA I/O OD, CMOS – Data I/O of serial I2C bus 5 RDYC I/O OD, CMOS – Combined ready output, high active and fault clear input and soft-off input, low active 6 FLT_N I/O OD, CMOS – Fault output, low active and soft-off input, low active Datasheet 7 v2.0 2020-03-26 Document Outline Table of contents 1 Block diagram 2 Related products 3 Pin configuration and functionality 3.1 Pin configuration 3.2 Pin functionality 3.3 Configurable parameters via I2C 4 Functional description 4.1 Start-up and fault clearing 4.2 Supply 4.3 Input side logic 4.4 I2C bus 4.5 Operating states 4.6 Measurement 4.7 Monitoring 4.8 Desaturation protection 4.8.1 DESAT behavior 4.9 Gate driver output 4.9.1 Turn-on behavior 4.9.2 Turn-off and fault turn-off behavior 4.9.2.1 Hard switching turn-off 4.9.2.2 Two-level turn-off 4.9.2.3 Soft turn-off 4.9.3 Active shut-down 4.9.4 Active Miller clamp 4.10 Short circuit clamping 5 Electrical parameters 5.1 Absolute maximum ratings 5.2 Thermal parameters 5.3 Operating parameters 5.4 Electrical characteristics 5.4.1 Voltage supply 5.4.2 Logic input and output 5.4.3 Gate driver 5.4.4 Active Miller clamp 5.4.5 Dynamic characteristics 5.4.6 Desaturation protection 5.4.7 Two-level turn-off 5.4.8 Soft-off current source 5.4.9 Over-temperature protection 5.4.10 ADC measurement 6 Insulation characteristics 6.1 Certified according to VDE 0884-11 and IEC 60747-17 reinforced insulation (planned) 6.2 Recognized under UL 1577 (planned) 7 Package information Revision history Disclaimer