Datasheet SAM9X60 SIP (Microchip) - 2

SAM9X60 SIP Features
• CPU – ARM926EJ-S Arm Thumb processor running up to 600 MHz – 32-Kbyte data cache, 32-Kbyte instruction cache, Memory Management Unit (MMU) • Memories – One 160-Kbyte internal ROM • 64-Kbyte internal ROM embedding a secure bootloader program supporting boot on NandFlash, SDCard, SPI or QSPI Flash. Bootloader features selectable by OTP bits. • 96-Kbyte ROM for NAND Flash BCH ECC table – DDR2-SDRAM memory up to 1 Gbit or 64-Mbit SDR-SDRAM memory, 16-bit data bus – One 64-Kbyte internal SRAM (SRAM0), single-cycle access at system speed – High Bandwidth Multi-port DDR2/LPDDR Controller (MPDDRC) – 8-bit External Bus Interface (EBI) supporting 8-bit NAND Flash connected on D16-D23 – NAND Flash Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code (PMECC) – One 11-Kbyte OTP memory for secure key storage with emulation mode (OTP bits are emulated by a 4- Kbyte SRAM (SRAM1)) • System Running up to 200 MHz – Power-on Reset cells, Reset Controller, Shutdown Controller, Periodic Interval Timer, Watchdog Timer running on internal low-power 32-kHz RC and Real Time Clock running on external crystal – Two internal trimmed RC oscillators: 32 kHz (low-power) and 12 MHz – Two selectable crystal oscillators: 32.768 kHz (low-power) and 8 to 50 MHz – One PLL for the system and one PLL optimized for USB high-speed operation (480 MHz) – One dual-port 16-channel DMA Controller (XDMAC) – Advanced Interrupt Controller (AIC) and Debug Unit (DBGU) – JTAG port with disable bit in OTP memory – Two programmable external clock signals • Low Power Modes – Backup mode with RTC, eight 32-bit general purpose backup registers, and Shutdown Controller to control the external power supply – Clock Generator and Power Management Controller – Software-programmable Ultra-Low Power modes: Very Slow Clock Operating Mode (ULP0), and No-Clock Operating Mode (ULP1) with fast wake-up capabilities – Software programmable power optimization capabilities • Peripherals – LCD Controller with overlay, alpha-blending, rotation, scaling and color conversion. Up to 1024 x 768 resolution – 2D Graphics Controller supporting Fill BLT, Copy BLT, Transparent BLT, Blend/Alpha BLT, ROP4 BLT (Raster Operations) and Command Ring Buffer – ITU-R BT. 601/656, up to 12-bit Image Sensor Interface (ISI) – One USB Device High Speed, three USB Host High Speed with dedicated On-Chip Transceivers – Two 10/100 Mbps Ethernet Mac Controller – Two 4-bit Secure Digital MultiMedia Card Controller (SDMMC) – Two CAN Controllers – One Quad I/O SPI Controller – Two three-channel 32-bit Timer/Counters – One high resolution (64-bit) Periodic Interval Timer – One Synchronous Serial Controller – One Inter-IC Sound (I²S) Multi-Channel Controller (I2SMCC) with TDM support – One Audio Class D Controller with Single-Ended (SE) or Bridge Tied Load (BTL) connection to power stage – One four-channel 16-bit PWM Controller © 2020 Microchip Technology Inc.
Datasheet
DS60001580B-page 2 Document Outline Scope Introduction Reference Documents Features Table of Contents 1. DDR2-SDRAM Features 2. SDR-SDRAM Features 3. Configuration Summary 4. Block Diagram 5. Chip Identifier 6. Package and Ballout 6.1. Packages 6.2. Ballout 7. Memories 8. Electrical Characteristics 8.1. Decoupling 8.2. Power Sequences 9. Mechanical Characteristics 9.1. 233-Ball TFBGA 9.2. 196-Ball TFBGA 10. Ordering Information 11. Revision History 11.1. DS60001580B - 02/2020 11.2. DS60001580A - 10/2019 The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service