Datasheet SAM9X60 SIP (Microchip) - 6
| 制造商 | Microchip |
| 描述 | SAM9X60 System-In-Package (SIP) MPU with up to 1 Gbit DDR2 SDRAM and up to 64 Mbits SDR-SDRAM |
| 页数 / 页 | 40 / 6 — SAM9X60 SIP. DDR2-SDRAM Features. Datasheet |
| 文件格式/大小 | PDF / 770 Kb |
| 文件语言 | 英语 |
SAM9X60 SIP. DDR2-SDRAM Features. Datasheet
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SAM9X60 SIP DDR2-SDRAM Features 1. DDR2-SDRAM Features
• Part Numbers: – 1-Gbit DDR2-SDRAM device (SAM9X60D1G-I): Winbond W971G16SG2-5I – 512-Mbit DDR2-SDRAM device (SAM9X60D5M-I): Winbond W975116KG2-5I • Power Supply: DDRM_VDD = 1.8V ±0.1V • Double Data Rate Architecture: Two Data Transfers per Clock Cycle • CAS Latency: 3 • Burst Length: 8 • Bi-Directional, Differential Data Strobes (DQS and DQSN) are Transmitted/Received with Data • Edge-Aligned with Read Data and Center-Aligned with Write Data • DLL Aligns DQ and DQS Transitions with Clock • Differential Clock Inputs (CLK and CLKN) • Data Masks (DM) for Write Data • Commands Entered on Each Positive CLK Edge, Data and Data Mask are Referenced to Both Edges of DQS • Auto-Refresh and Self-Refresh Modes • Precharged Power-Down and Active Power-Down • Write Data Mask • Write Latency = Read Latency - 1 (WL = RL - 1) • Interface: SSTL_18 © 2020 Microchip Technology Inc.
Datasheet
DS60001580B-page 6 Document Outline Scope Introduction Reference Documents Features Table of Contents 1. DDR2-SDRAM Features 2. SDR-SDRAM Features 3. Configuration Summary 4. Block Diagram 5. Chip Identifier 6. Package and Ballout 6.1. Packages 6.2. Ballout 7. Memories 8. Electrical Characteristics 8.1. Decoupling 8.2. Power Sequences 9. Mechanical Characteristics 9.1. 233-Ball TFBGA 9.2. 196-Ball TFBGA 10. Ordering Information 11. Revision History 11.1. DS60001580B - 02/2020 11.2. DS60001580A - 10/2019 The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service
• Part Numbers: – 1-Gbit DDR2-SDRAM device (SAM9X60D1G-I): Winbond W971G16SG2-5I – 512-Mbit DDR2-SDRAM device (SAM9X60D5M-I): Winbond W975116KG2-5I • Power Supply: DDRM_VDD = 1.8V ±0.1V • Double Data Rate Architecture: Two Data Transfers per Clock Cycle • CAS Latency: 3 • Burst Length: 8 • Bi-Directional, Differential Data Strobes (DQS and DQSN) are Transmitted/Received with Data • Edge-Aligned with Read Data and Center-Aligned with Write Data • DLL Aligns DQ and DQS Transitions with Clock • Differential Clock Inputs (CLK and CLKN) • Data Masks (DM) for Write Data • Commands Entered on Each Positive CLK Edge, Data and Data Mask are Referenced to Both Edges of DQS • Auto-Refresh and Self-Refresh Modes • Precharged Power-Down and Active Power-Down • Write Data Mask • Write Latency = Read Latency - 1 (WL = RL - 1) • Interface: SSTL_18 © 2020 Microchip Technology Inc.
Datasheet
DS60001580B-page 6 Document Outline Scope Introduction Reference Documents Features Table of Contents 1. DDR2-SDRAM Features 2. SDR-SDRAM Features 3. Configuration Summary 4. Block Diagram 5. Chip Identifier 6. Package and Ballout 6.1. Packages 6.2. Ballout 7. Memories 8. Electrical Characteristics 8.1. Decoupling 8.2. Power Sequences 9. Mechanical Characteristics 9.1. 233-Ball TFBGA 9.2. 196-Ball TFBGA 10. Ordering Information 11. Revision History 11.1. DS60001580B - 02/2020 11.2. DS60001580A - 10/2019 The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service