Datasheet SAM9X35 (Microchip)

SAM9X35 Atmel | SMART ARM-based Embedded MPU DATASHEET Description
The SAM9X35 is a member of the Atmel® | SMART series of 400 MHz ARM926EJ-S™ embedded microprocessor units. This MPU features an extensive peripheral set and high bandwidth architecture for industrial applications that require refined user interfaces and high-speed communication. The SAM9X35 features a graphics LCD controller with 4-layer overlay and 2D acceleration (picture-in-picture, alpha-blending, scaling, rotation, color conversion), and a 10-bit ADC that supports 4-wire or 5-wire resistive touchscreen panels. Networking/connectivity peripherals include two 2.0A/B compatible Controller Area Network (CAN) interfaces and an IEEE Std 802.3-compatible 10/100 Mbps Ethernet MAC. Multiple communication interfaces include a soft modem supporting exclusively the Conexant SmartDAA line driver, HS USB Device and Host, FS USB Host, two HS SDCard/SDIO/MMC interfaces, USARTs, SPIs, I2S, TWIs and 10-bit ADC. The 10-layer bus matrix associated with 2 x 8 central DMA channels as well as dedicated DMAs to support the high-speed connectivity peripherals ensure uninterrupted data transfer with minimum processor overhead. The External Bus Interface incorporates controllers for 4-bank and 8-bank DDR2/LPDDR, SDRAM/LPSDRAM, static memories, as well as specific circuitry for MLC/SLC NAND Flash with integrated ECC up to 24 bits. The SAM9X35 is available in a 217-ball BGA package with 0.8 mm ball pitch. Atmel-11055F-ATARM-SAM9X35-Datasheet_31-Aug-15 Document Outline Description Features 1. Block Diagram 2. Signal Description 3. Package and Pinout 3.1 Overview of the 217-ball BGA Package 3.2 I/O Description 3.2.1 Reset State 3.3 217-ball BGA Package Pinout 4. Power Considerations 4.1 Power Supplies 5. Memories 5.1 Memory Mapping 5.2 Embedded Memories 5.2.1 Internal SRAM 5.2.2 Internal ROM 5.3 External Memories 5.3.1 External Bus Interface 5.3.2 Static Memory Controller 5.3.3 DDR2SDR Controller 6. System Controller 6.1 Chip Identification 6.2 Backup Area 7. Peripherals 7.1 Peripheral Mapping 7.2 Peripheral Identifiers 7.3 Peripheral Signal Multiplexing on I/O Lines 8. ARM926EJ-S™ 8.1 Description 8.2 Embedded Characteristics 8.3 Block Diagram 8.4 ARM9EJ-S Processor 8.4.1 ARM9EJ-S Operating States 8.4.2 Switching State 8.4.3 Instruction Pipelines 8.4.4 Memory Access 8.4.5 Jazelle Technology 8.4.6 ARM9EJ-S Operating Modes 8.4.7 ARM9EJ-S Registers 8.4.7.1 Status Registers 8.4.7.2 Exceptions 8.4.8 ARM Instruction Set Overview 8.4.9 New ARM Instruction Set 8.4.10 Thumb Instruction Set Overview 8.5 CP15 Coprocessor 8.5.1 CP15 Registers Access 8.6 Memory Management Unit (MMU) 8.6.1 Access Control Logic 8.6.2 Translation Look-aside Buffer (TLB) 8.6.3 Translation Table Walk Hardware 8.6.4 MMU Faults 8.7 Caches and Write Buffer 8.7.1 Instruction Cache (ICache) 8.7.2 Data Cache (DCache) and Write Buffer 8.7.2.1 DCache 8.7.2.2 Write Buffer 8.8 Bus Interface Unit 8.8.1 Supported Transfers 8.8.2 Thumb Instruction Fetches 8.8.3 Address Alignment 9. Debug and Test 9.1 Description 9.2 Embedded Characteristics 9.3 Block Diagram 9.4 Application Examples 9.4.1 Debug Environment 9.4.2 Test Environment 9.5 Debug and Test Pin Description 9.6 Functional Description 9.6.1 Test Pin 9.6.2 EmbeddedICE™ 9.6.3 JTAG Signal Description 9.6.4 Debug Unit 9.6.5 IEEE 1149.1 JTAG Boundary Scan 9.6.6 JTAG ID Code Register 10. Boot Strategies 10.1 ROM Code 10.2 Flow Diagram 10.3 Chip Setup 10.4 NVM Boot 10.4.1 NVM Boot Sequence 10.4.2 NVM Bootloader Program Description 10.4.3 Valid Code Detection 10.4.3.1 ARM Exception Vectors Check 10.4.3.2 boot.bin File Check 10.4.4 Detailed Memory Boot Procedures 10.4.4.1 NAND Flash Boot: NAND Flash Detection NAND Flash Specific Header Detection ONFI 2.2 Parameters 10.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction 10.4.4.3 SD Card Boot Supported SD Card Devices 10.4.4.4 SPI Flash Boot Supported DataFlash Devices Supported Serial Flash Devices 10.4.4.5 TWI EEPROM Boot Supported TWI EEPROM Devices 10.4.5 Hardware and Software Constraints 10.5 SAM-BA Monitor 10.5.1 Command List 10.5.2 DBGU Serial Port 10.5.2.1 Supported External Crystal/External Clocks 10.5.2.2 Xmodem Protocol 10.5.3 USB Device Port 10.5.3.1 Supported External Crystal / External Clocks 10.5.3.2 USB Class 10.5.3.3 Enumeration Process 10.5.3.4 Communication Endpoints 11. Boot Sequence Controller (BSC) 11.1 Description 11.2 Embedded Characteristics 11.3 Product Dependencies 11.4 Boot Sequence Controller (BSC) Registers User Interface 11.4.1 Boot Sequence Controller Configuration Register 12. Advanced Interrupt Controller (AIC) 12.1 Description 12.2 Embedded Characteristics 12.6 I/O Line Description 12.7 Product Dependencies 12.7.1 I/O Lines 12.7.2 Power Management 12.7.3 Interrupt Sources 12.8 Functional Description 12.8.1 Interrupt Source Control 12.8.1.1 Interrupt Source Mode 12.8.1.2 Interrupt Source Enabling 12.8.1.3 Interrupt Clearing and Setting 12.8.1.4 Interrupt Status 12.8.2 Interrupt Latencies 12.8.3 Normal Interrupt 12.8.3.1 Priority Controller 12.8.3.2 Interrupt Nesting 12.8.3.3 Interrupt Vectoring 12.8.3.4 Interrupt Handlers 12.8.4 Fast Interrupt 12.8.4.1 Fast Interrupt Source 12.8.4.2 Fast Interrupt Control 12.8.4.3 Fast Interrupt Vectoring 12.8.4.4 Fast Interrupt Handlers 12.8.5 Protect Mode 12.8.6 Spurious Interrupt 12.8.7 General Interrupt Mask 12.8.8 Register Write Protection 12.9 Advanced Interrupt Controller (AIC) User Interface 12.9.1 AIC Source Mode Register 12.9.2 AIC Source Vector Register 12.9.3 AIC Interrupt Vector Register 12.9.4 AIC FIQ Vector Register 12.9.5 AIC Interrupt Status Register 12.9.6 AIC Interrupt Pending Register 12.9.7 AIC Interrupt Mask Register 12.9.8 AIC Core Interrupt Status Register 12.9.9 AIC Interrupt Enable Command Register 12.9.10 AIC Interrupt Disable Command Register 12.9.11 AIC Interrupt Clear Command Register 12.9.12 AIC Interrupt Set Command Register 12.9.13 AIC End of Interrupt Command Register 12.9.14 AIC Spurious Interrupt Vector Register 12.9.15 AIC Debug Control Register 12.9.16 AIC Fast Forcing Enable Register 12.9.17 AIC Fast Forcing Disable Register 12.9.18 AIC Fast Forcing Status Register 12.9.19 AIC Write Protection Mode Register 12.9.20 AIC Write Protection Status Register 13. Reset Controller (RSTC) 13.1 Description 13.2 Embedded Characteristics 13.3 Block Diagram 13.4 Functional Description 13.4.1 Reset Controller Overview 13.4.2 NRST Manager 13.4.2.1 NRST Signal 13.4.2.2 NRST External Reset Control 13.4.3 BMS Sampling 13.4.4 Reset States 13.4.4.1 General Reset 13.4.4.2 Wake-up Reset 13.4.4.3 User Reset 13.4.4.4 Software Reset 13.4.4.5 Watchdog Reset 13.4.5 Reset State Priorities 13.5 Reset Controller (RSTC) User Interface 13.5.1 Reset Controller Control Register 13.5.2 Reset Controller Status Register 13.5.3 Reset Controller Mode Register 14. Real-time Clock (RTC) 14.1 Description 14.2 Embedded Characteristics 14.3 Block Diagram 14.4 Product Dependencies 14.4.1 Power Management 14.4.2 Interrupt 14.5 Functional Description 14.5.1 Reference Clock 14.5.2 Timing 14.5.3 Alarm 14.5.4 Error Checking when Programming 14.5.5 Updating Time/Calendar 14.6 Real-time Clock (RTC) User Interface 14.6.1 RTC Control Register 14.6.2 RTC Mode Register 14.6.3 RTC Time Register 14.6.4 RTC Calendar Register 14.6.5 RTC Time Alarm Register 14.6.6 RTC Calendar Alarm Register 14.6.7 RTC Status Register 14.6.8 RTC Status Clear Command Register 14.6.9 RTC Interrupt Enable Register 14.6.10 RTC Interrupt Disable Register 14.6.11 RTC Interrupt Mask Register 14.6.12 RTC Valid Entry Register 15. Periodic Interval Timer (PIT) 15.1 Description 15.2 Embedded Characteristics 15.3 Block Diagram 15.4 Functional Description 15.5 Periodic Interval Timer (PIT) User Interface 15.5.1 Periodic Interval Timer Mode Register 15.5.2 Periodic Interval Timer Status Register 15.5.3 Periodic Interval Timer Value Register 15.5.4 Periodic Interval Timer Image Register 16. Watchdog Timer (WDT) 16.1 Description 16.2 Embedded Characteristics 16.3 Block Diagram 16.4 Functional Description 16.5 Watchdog Timer (WDT) User Interface 16.5.1 Watchdog Timer Control Register 16.5.2 Watchdog Timer Mode Register 16.5.3 Watchdog Timer Status Register 17. Shutdown Controller (SHDWC) 17.1 Description 17.2 Embedded Characteristics 17.3 Block Diagram 17.4 I/O Lines Description 17.5 Product Dependencies 17.5.1 Power Management 17.6 Functional Description 17.6.1 Wake-up Inputs 17.7 Shutdown Controller (SHDWC) User Interface 17.7.1 Shutdown Control Register 17.7.2 Shutdown Mode Register 17.7.3 Shutdown Status Register 18. General Purpose Backup Registers (GPBR) 18.1 Description 18.2 Embedded Characteristics 18.3 General Purpose Backup Registers (GPBR) User Interface 18.3.1 General Purpose Backup Register x 19. Slow Clock Controller (SCKC) 19.1 Description 19.2 Embedded Characteristics 19.3 Block Diagram 19.4 Functional Description 19.4.1 Switching from Embedded 32 kHz RC Oscillator to 32.768 kHz Crystal Oscillator 19.4.2 Bypassing the 32.768 kHz Crystal Oscillator 19.4.3 Switching from 32.768 kHz Crystal Oscillator to Embedded 32 kHz RC Oscillator 19.5 Slow Clock Controller (SCKC) User Interface 19.5.1 Slow Clock Controller Configuration Register 20. Clock Generator 20.1 Description 20.2 Embedded Characteristics 20.3 Block Diagram 20.4 Slow Clock 20.4.1 Embedded 32 kHz (typical) RC Oscillator 20.4.2 32.768 kHz Crystal Oscillator 20.5 Main Clock 20.5.2 12 to 16 MHz Crystal Oscillator 20.5.3 Main Clock Source Selection 20.5.4 Bypassing the 12 to 16 MHz Crystal Oscillator 20.5.5 Main Clock Frequency Counter 20.5.6 Switching Main Clock Between the RC Oscillator and the Crystal Oscillator 21. Power Management Controller (PMC) 21.1 Description 21.2 Embedded Characteristics 21.3 Block Diagram 21.4 Master Clock Controller 21.8 DDR2/LPDDR Clock 21.9 Software Modem Clock 21.10 Fast Wake-up from Backup Mode 21.11 Peripheral Clock Controller 21.12 Programmable Clock Controller 21.13 Main Clock Failure Detector 21.14 Programming Sequence 21.15 Clock Switching Details 21.15.1 Master Clock Switching Timings 21.15.2 Clock Switching Waveforms 21.16 Register Write Protection 21.17 Power Management Controller (PMC) User Interface 21.17.1 PMC System Clock Enable Register 21.17.2 PMC System Clock Disable Register 21.17.3 PMC System Clock Status Register 21.17.4 PMC Peripheral Clock Enable Register 21.17.5 PMC Peripheral Clock Disable Register 21.17.6 PMC Peripheral Clock Status Register 21.17.7 PMC UTMI Clock Configuration Register 21.17.8 PMC Clock Generator Main Oscillator Register 21.17.9 PMC Clock Generator Main Clock Frequency Register 21.17.10 PMC Clock Generator PLLA Register 21.17.11 PMC Master Clock Register 21.17.12 PMC USB Clock Register 21.17.13 PMC SMD Clock Register 21.17.14 PMC Programmable Clock Register 21.17.15 PMC Interrupt Enable Register 21.17.16 PMC Interrupt Disable Register 21.17.17 PMC Status Register 21.17.18 PMC Interrupt Mask Register 21.17.19 PLL Charge Pump Current Register 21.17.20 PMC Write Protection Mode Register 21.17.21 PMC Write Protection Status Register 21.17.22 PMC Peripheral Control Register 22. Parallel Input/Output Controller (PIO) 22.1 Description 22.2 Embedded Characteristics 22.3 Block Diagram 22.4 Product Dependencies 22.4.1 Pin Multiplexing 22.4.2 External Interrupt Lines 22.4.3 Power Management 22.4.4 Interrupt Sources 22.5 Functional Description 22.5.1 Pull-up and Pull-down Resistor Control 22.5.2 I/O Line or Peripheral Function Selection 22.5.3 Peripheral A or B or C or D Selection 22.5.4 Output Control 22.5.5 Synchronous Data Output 22.5.6 Multi-Drive Control (Open Drain) 22.5.7 Output Line Timings 22.5.8 Inputs 22.5.9 Input Glitch and Debouncing Filters 22.5.10 Input Edge/Level Interrupt 22.5.11 Programmable I/O Delays 22.5.12 Programmable I/O Drive 22.5.13 Programmable Schmitt Trigger 22.5.14 I/O Lines Programming Example 22.5.15 Register Write Protection 22.6 Parallel Input/Output Controller (PIO) User Interface 22.6.1 PIO Enable Register 22.6.2 PIO Disable Register 22.6.3 PIO Status Register 22.6.4 PIO Output Enable Register 22.6.5 PIO Output Disable Register 22.6.6 PIO Output Status Register 22.6.7 PIO Input Filter Enable Register 22.6.8 PIO Input Filter Disable Register 22.6.9 PIO Input Filter Status Register 22.6.10 PIO Set Output Data Register 22.6.11 PIO Clear Output Data Register 22.6.12 PIO Output Data Status Register 22.6.13 PIO Pin Data Status Register 22.6.14 PIO Interrupt Enable Register 22.6.15 PIO Interrupt Disable Register 22.6.16 PIO Interrupt Mask Register 22.6.17 PIO Interrupt Status Register 22.6.18 PIO Multi-driver Enable Register 22.6.19 PIO Multi-driver Disable Register 22.6.20 PIO Multi-driver Status Register 22.6.21 PIO Pull-Up Disable Register 22.6.22 PIO Pull-Up Enable Register 22.6.23 PIO Pull-Up Status Register 22.6.24 PIO Peripheral ABCD Select Register 1 22.6.25 PIO Peripheral ABCD Select Register 2 22.6.26 PIO Input Filter Slow Clock Disable Register 22.6.27 PIO Input Filter Slow Clock Enable Register 22.6.28 PIO Input Filter Slow Clock Status Register 22.6.29 PIO Slow Clock Divider Debouncing Register 22.6.30 PIO Pad Pull-Down Disable Register 22.6.31 PIO Pad Pull-Down Enable Register 22.6.32 PIO Pad Pull-Down Status Register 22.6.33 PIO Output Write Enable Register 22.6.34 PIO Output Write Disable Register 22.6.35 PIO Output Write Status Register 22.6.36 PIO Additional Interrupt Modes Enable Register 22.6.37 PIO Additional Interrupt Modes Disable Register 22.6.38 PIO Additional Interrupt Modes Mask Register 22.6.39 PIO Edge Select Register 22.6.40 PIO Level Select Register 22.6.41 PIO Edge/Level Status Register 22.6.42 PIO Falling Edge/Low-Level Select Register 22.6.43 PIO Rising Edge/High-Level Select Register 22.6.44 PIO Fall/Rise - Low/High Status Register 22.6.45 PIO Write Protection Mode Register 22.6.46 PIO Write Protection Status Register 22.6.47 PIO Schmitt Trigger Register 22.6.48 PIO I/O Delay Register 22.6.49 PIO I/O Drive Register 1 22.6.50 PIO I/O Drive Register 2 23. Debug Unit (DBGU) 23.1 Description 23.2 Embedded Characteristics 23.3 Block Diagram 23.4 Product Dependencies 23.4.1 I/O Lines 23.4.2 Power Management 23.4.3 Interrupt Source 23.5 UART Operations 23.5.1 Baud Rate Generator 23.5.2 Receiver 23.5.2.1 Receiver Reset, Enable and Disable 23.5.2.2 Start Detection and Data Sampling 23.5.2.3 Receiver Ready 23.5.2.4 Receiver Overrun 23.5.2.5 Parity Error 23.5.2.6 Receiver Framing Error 23.5.3 Transmitter 23.5.3.1 Transmitter Reset, Enable and Disable 23.5.3.2 Transmit Format 23.5.3.3 Transmitter Control 23.5.4 DMA Support 23.5.5 Test Modes 23.5.6 Debug Communication Channel Support 23.5.7 Chip Identifier 23.5.8 ICE Access Prevention 23.6 Debug Unit (DBGU) User Interface 23.6.1 Debug Unit Control Register 23.6.2 Debug Unit Mode Register 23.6.3 Debug Unit Interrupt Enable Register 23.6.4 Debug Unit Interrupt Disable Register 23.6.5 Debug Unit Interrupt Mask Register 23.6.6 Debug Unit Status Register 23.6.7 Debug Unit Receive Holding Register 23.6.8 Debug Unit Transmit Holding Register 23.6.9 Debug Unit Baud Rate Generator Register 23.6.10 Debug Unit Chip ID Register 23.6.11 Debug Unit Chip ID Extension Register 23.6.12 Debug Unit Force NTRST Register 24. Bus Matrix (MATRIX) 24.1 Description 24.2 Embedded Characteristics 24.2.1 Matrix Masters 24.2.2 Matrix Slaves 24.2.3 Master to Slave Access 24.3 Memory Mapping 24.4 Special Bus Granting Mechanism 24.4.1 No Default Master 24.4.2 Last Access Master 24.4.3 Fixed Default Master 24.5 Arbitration 24.5.1 Arbitration Scheduling 24.5.1.1 Undefined Length Burst Arbitration 24.5.1.2 Slot Cycle Limit Arbitration 24.5.2 Arbitration Priority Scheme 24.5.2.1 Fixed Priority Arbitration 24.5.2.2 Round-Robin Arbitration 24.6 Register Write Protection 24.7 Bus Matrix (MATRIX) User Interface 24.7.1 Bus Matrix Master Configuration Registers 24.7.2 Bus Matrix Slave Configuration Registers 24.7.3 Bus Matrix Priority Registers A For Slaves 24.7.4 Bus Matrix Priority Registers B For Slaves 24.7.5 Bus Matrix Master Remap Control Register 24.7.6 EBI Chip Select Assignment Register 24.7.7 Write Protection Mode Register 24.7.8 Write Protection Status Register 25. External Bus Interface (EBI) 25.1 Description 25.2 Embedded Characteristics 25.3 EBI Block Diagram 25.4 I/O Lines Description 25.5 Application Example 25.5.1 Hardware Interface 25.5.2 Product Dependencies 25.5.2.1 I/O Lines 25.5.3 Functional Description 25.5.3.1 Bus Multiplexing 25.5.3.2 Pull-up and Pull-down Control 25.5.3.3 Drive Level and Delay Control 25.5.3.4 Power supplies 25.5.3.5 Static Memory Controller 25.5.3.6 DDR2SDRAM Controller 25.5.3.7 Programmable Multibit ECC Controller 25.5.3.8 NAND Flash Support External Bus Interface NAND Flash Signals 25.5.4 Implementation Examples 25.5.4.1 2x8-bit DDR2 on EBI Software Configuration - 2x8-bit DDR2 on EBI 25.5.4.2 16-bit LPDDR on EBI Software Configuration - 16-bit LPDDR on EBI 25.5.4.3 16-bit SDRAM on EBI Software Configuration - 16-bit SDRAM on EBI 25.5.4.4 2x16-bit SDRAM on EBI Software Configuration - 2x16-bit SDRAM on EBI 25.5.4.5 8-bit NAND Flash with NFD0_ON_D16 = 0 Software Configuration - 8-bit NAND Flash with NFD0_ON_D16 = 0 25.5.4.6 16-bit NAND Flash with NFD0_ON_D16 = 0 Software Configuration - 16-bit NAND Flash with NFD0_ON_D16 = 0 25.5.4.7 8-bit NAND Flash with NFD0_ON_D16 = 1 Software Configuration - 8-bit NAND Flash with NFD0_ON_D16 = 1 25.5.4.8 16-bit NAND Flash with NFD0_ON_D16 = 1 Software Configuration - 16-bit NAND Flash with NFD0_ON_D16 = 1 25.5.4.9 NOR Flash on NCS0 Software Configuration - NOR Flash on NCS0 26. Programmable Multibit ECC Controller (PMECC) 26.1 Description 26.2 Embedded Characteristics 26.3 Block Diagram 26.4 Functional Description 26.4.1 MLC/SLC Write Page Operation using PMECC 26.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set 26.4.1.2 MLC/SLC Write Operation with Spare Area Disabled 26.4.2 MLC/SLC Read Page Operation using PMECC 26.4.2.1 MLC/SLC Read Operation with Spare Decoding 26.4.2.2 MLC/SLC Read Operation 26.4.2.3 MLC/SLC User Read ECC Area 26.5 Software Implementation 26.5.1 Remainder Substitution Procedure 26.5.2 Find the Error Location Polynomial Sigma(x) 26.5.3 Find the Error Position 26.6 Programmable Multibit ECC Controller (PMECC) User Interface 26.6.1 PMECC Configuration Register 26.6.2 PMECC Spare Area Size Register 26.6.3 PMECC Start Address Register 26.6.4 PMECC End Address Register 26.6.5 PMECC Clock Control Register 26.6.6 PMECC Control Register 26.6.7 PMECC Status Register 26.6.8 PMECC Interrupt Enable Register 26.6.9 PMECC Interrupt Disable Register 26.6.10 PMECC Interrupt Mask Register 26.6.11 PMECC Interrupt Status Register 26.6.12 PMECC ECC x Register 26.6.13 PMECC Remainder x Register 27. Programmable Multibit ECC Error Location Controller (PMERRLOC) 27.1 Description 27.2 Embedded Characteristics 27.3 Block Diagram 27.4 Functional Description 27.5 Programmable Multibit ECC Error Location Controller (PMERRLOC) User Interface 27.5.1 Error Location Configuration Register 27.5.2 Error Location Primitive Register 27.5.3 Error Location Enable Register 27.5.4 Error Location Disable Register 27.5.5 Error Location Status Register 27.5.6 Error Location Interrupt Enable Register 27.5.7 Error Location Interrupt Disable Register 27.5.8 Error Location Interrupt Mask Register 27.5.9 Error Location Interrupt Status Register 27.5.10 Error Location SIGMAx Register 27.5.11 PMECC Error Locationx Register 28. Static Memory Controller (SMC) 28.1 Description 28.2 Embedded Characteristics 28.3 I/O Lines Description 28.4 Multiplexed Signals 28.5 Application Example 28.5.1 Hardware Interface 28.6 Product Dependencies 28.6.1 I/O Lines 28.7 External Memory Mapping 28.8 Connection to External Devices 28.8.1 Data Bus Width 28.8.2 Byte Write or Byte Select Access 28.8.2.1 Byte Write Access 28.8.2.2 Byte Select Access 28.8.2.3 Signal Multiplexing 28.9 Standard Read and Write Protocols 28.9.1 Read Waveforms 28.9.1.1 NRD Waveform 28.9.1.2 NCS Waveform 28.9.1.3 Read Cycle 28.9.1.4 Null Delay Setup and Hold 28.9.1.5 Null Pulse 28.9.2 Read Mode 28.9.2.1 Read is Controlled by NRD (READ_MODE = 1) 28.9.2.2 Read is Controlled by NCS (READ_MODE = 0) 28.9.3 Write Waveforms 28.9.3.1 NWE Waveforms 28.9.3.2 NCS Waveforms 28.9.3.3 Write Cycle 28.9.3.4 Null Delay Setup and Hold 28.9.3.5 Null Pulse 28.9.4 Write Mode 28.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1): 28.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0) 28.9.5 Coding Timing Parameters 28.9.6 Reset Values of Timing Parameters 28.9.7 Usage Restriction 28.10 Automatic Wait States 28.10.1 Chip Select Wait States 28.10.2 Early Read Wait State 28.10.3 Reload User Configuration Wait State 28.10.3.1 User Procedure 28.10.3.2 Slow Clock Mode Transition 28.10.4 Read to Write Wait State 28.11 Data Float Wait States 28.11.1 READ_MODE 28.11.2 TDF Optimization Enabled (TDF_MODE = 1) 28.11.3 TDF Optimization Disabled (TDF_MODE = 0) 28.12 External Wait 28.12.1 Restriction 28.12.2 Frozen Mode 28.12.3 Ready Mode 28.12.4 NWAIT Latency and Read/Write Timings 28.13 Slow Clock Mode 28.13.1 Slow Clock Mode Waveforms 28.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode 28.14 Asynchronous Page Mode 28.14.1 Protocol and Timings in Page Mode 28.14.2 Byte Access Type in Page Mode 28.14.3 Page Mode Restriction 28.14.4 Sequential and Non-sequential Accesses 28.15 Register Write Protection 28.16 Static Memory Controller (SMC) User Interface 28.16.1 SMC Setup Register 28.16.2 SMC Pulse Register 28.16.3 SMC Cycle Register 28.16.4 SMC Mode Register 28.16.5 SMC Write Protection Mode Register 28.16.6 SMC Write Protection Status Register 29. DDR SDR SDRAM Controller (DDRSDRC) 29.1 Description 29.2 Embedded Characteristics 29.3 DDRSDRC Module Diagram 29.4 Initialization Sequence 29.4.1 SDR-SDRAM Initialization 29.4.2 Low-power DDR1-SDRAM Initialization 29.4.3 DDR2-SDRAM Initialization 29.5 Functional Description 29.5.1 SDRAM Controller Write Cycle 29.5.2 SDRAM Controller Read Cycle 29.5.3 Refresh (Auto-refresh Command) 29.5.4 Power Management 29.5.4.1 Self Refresh Mode 29.5.4.2 Power-down Mode 29.5.4.3 Deep Power-down Mode 29.5.4.4 Reset Mode 29.5.5 Multi-port Functionality 29.5.6 Register Write Protection 29.6 Software Interface/SDRAM Organization, Address Mapping 29.6.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Four Banks 29.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks 29.6.3 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width 29.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface 29.7.1 DDRSDRC Mode Register 29.7.2 DDRSDRC Refresh Timer Register 29.7.3 DDRSDRC Configuration Register 29.7.4 DDRSDRC Timing Parameter 0 Register 29.7.5 DDRSDRC Timing Parameter 1 Register 29.7.6 DDRSDRC Timing Parameter 2 Register 29.7.7 DDRSDRC Low-power Register 29.7.8 DDRSDRC Memory Device Register 29.7.9 DDRSDRC DLL Register 29.7.10 DDRSDRC High Speed Register 29.7.11 DDRSDRC Write Protection Mode Register 29.7.12 DDRSDRC Write Protection Status Register 30. DMA Controller (DMAC) 30.1 Description 30.2 Embedded Characteristics 30.3 DMA Controller Peripheral Connections 30.3.1 DMA Controller 0 30.3.2 DMA Controller 1 30.4 Block Diagram 30.5 Product Dependencies 30.5.1 Interrupt Sources 30.6 Functional Description 30.6.1 Basic Definitions 30.6.2 Memory Peripherals 30.6.3 Handshaking Interface 30.6.3.1 Software Handshaking 30.6.4 DMAC Transfer Types 30.6.4.1 Multi-buffer Transfers 30.6.4.2 Programming DMAC for Multiple Buffer Transfers 30.6.4.3 Ending Multi-buffer Transfers 30.6.5 Programming a Channel 30.6.5.1 Programming Examples 30.6.6 Disabling a Channel Prior to Transfer Completion 30.6.6.1 Abnormal Transfer Termination 30.6.7 Register Write Protection 30.7 DMAC Software Requirements 30.8 DMA Controller (DMAC) User Interface 30.8.1 DMAC Global Configuration Register 30.8.2 DMAC Enable Register 30.8.3 DMAC Software Single Request Register 30.8.4 DMAC Software Chunk Transfer Request Register 30.8.5 DMAC Software Last Transfer Flag Register 30.8.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register 30.8.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register 30.8.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register 30.8.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register 30.8.10 DMAC Channel Handler Enable Register 30.8.11 DMAC Channel Handler Disable Register 30.8.12 DMAC Channel Handler Status Register 30.8.13 DMAC Channel x [x = 0..7] Source Address Register 30.8.14 DMAC Channel x [x = 0..7] Destination Address Register 30.8.15 DMAC Channel x [x = 0..7] Descriptor Address Register 30.8.16 DMAC Channel x [x = 0..7] Control A Register 30.8.17 DMAC Channel x [x = 0..7] Control B Register 30.8.18 DMAC Channel x [x = 0..7] Configuration Register 30.8.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register 30.8.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register 30.8.21 DMAC Write Protection Mode Register 30.8.22 DMAC Write Protection Status Register 31. USB High Speed Device Port (UDPHS) 31.1 Description 31.2 Embedded Characteristics 31.3 Block Diagram 31.4 Typical Connection 31.5 Product Dependencies 31.5.1 Power Management 31.5.2 Interrupt Sources 31.6 Functional Description 31.6.1 UTMI transceivers Sharing 31.6.2 USB V2.0 High Speed Device Port Introduction 31.6.3 USB V2.0 High Speed Transfer Types 31.6.4 USB Transfer Event Definitions 31.6.5 USB V2.0 High Speed BUS Transactions 31.6.6 Endpoint Configuration 31.6.7 DPRAM Management 31.6.8 Transfer With DMA 31.6.9 Transfer Without DMA 31.6.10 Handling Transactions with USB V2.0 Device Peripheral 31.6.10.1 Setup Transaction 31.6.10.2 NYET 31.6.10.3 Data IN Bulk IN or Interrupt IN Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host) Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) Isochronous IN High Bandwidth Isochronous Endpoint Handling: IN Example 31.6.10.4 Data OUT Bulk OUT or Interrupt OUT Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device) Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device) High Bandwidth Isochronous Endpoint OUT Isochronous Endpoint Handling: OUT Example 31.6.10.5 STALL 31.6.11 Speed Identification 31.6.12 USB V2.0 High Speed Global Interrupt 31.6.13 Endpoint Interrupts 31.6.14 Power Modes 31.6.14.1 Controlling Device States 31.6.14.2 Not Powered State 31.6.14.3 Entering Attached State 31.6.14.4 From Powered State to Default State (Reset) 31.6.14.5 From Default State to Address State (Address Assigned) 31.6.14.6 From Address State to Configured State (Device Configured) 31.6.14.7 Entering Suspend State (Bus Activity) 31.6.14.8 Receiving a Host Resume 31.6.14.9 Sending an External Resume 31.6.15 Test Mode 31.7 USB High Speed Device Port (UDPHS) User Interface 31.7.1 UDPHS Control Register 31.7.2 UDPHS Frame Number Register 31.7.3 UDPHS Interrupt Enable Register 31.7.4 UDPHS Interrupt Status Register 31.7.5 UDPHS Clear Interrupt Register 31.7.6 UDPHS Endpoints Reset Register 31.7.7 UDPHS Test Register 31.7.8 UDPHS Endpoint Configuration Register 31.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) 31.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints) 31.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) 31.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint) 31.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) 31.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint) 31.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) 31.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint) 31.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) 31.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint) 31.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) 31.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint) 31.7.21 UDPHS DMA Channel Transfer Descriptor 31.7.22 UDPHS DMA Next Descriptor Address Register 31.7.23 UDPHS DMA Channel Address Register 31.7.24 UDPHS DMA Channel Control Register 31.7.25 UDPHS DMA Channel Status Register 32. USB Host High Speed Port (UHPHS) 32.1 Description 32.2 Embedded Characteristics 32.3 Block Diagram 32.4 Typical Connection 32.5 Product Dependencies 32.5.1 I/O Lines 32.5.2 Power Management 32.5.3 Interrupt Sources 32.6 Functional Description 32.6.1 UTMI Transceivers Sharing 32.6.2 EHCI 32.6.3 OHCI 33. High Speed Multimedia Card Interface (HSMCI) 33.1 Description 33.2 Embedded Characteristics 33.3 Block Diagram 33.4 Application Block Diagram 33.5 Pin Name List 33.6 Product Dependencies 33.6.1 I/O Lines 33.6.2 Power Management 33.6.3 Interrupt Sources 33.7 Bus Topology 33.8 High Speed MultiMedia Card Operations 33.8.1 Command - Response Operation 33.8.2 Data Transfer Operation 33.8.3 Read Operation 33.8.4 Write Operation 33.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller 33.8.6 READ_SINGLE_BLOCK Operation using DMA Controller 33.8.6.1 Block Length is Multiple of 4 33.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (HSMCI_DMA.ROPT = 0) 33.8.6.3 Block Length is Not Multiple of 4, with Padding Value (HSMCI_DMA.ROPT = 1) 33.8.7 WRITE_MULTIPLE_BLOCK 33.8.7.1 One Block per Descriptor 33.8.8 READ_MULTIPLE_BLOCK 33.8.8.1 Block Length is a Multiple of 4 33.8.8.2 Block Length is Not Multiple of 4 (HSMCI_DMA.ROPT = 0) 33.8.8.3 Block Length is Not a Multiple of 4 (HSMCI_DMA.ROPT = 1) 33.9 SD/SDIO Card Operation 33.9.1 SDIO Data Transfer Type 33.9.2 SDIO Interrupts 33.10 CE-ATA Operation 33.10.1 Executing an ATA Polling Command 33.10.2 Executing an ATA Interrupt Command 33.10.3 Aborting an ATA Command 33.10.4 CE-ATA Error Recovery 33.11 HSMCI Boot Operation Mode 33.11.1 Boot Procedure, Processor Mode 33.11.2 Boot Procedure DMA Mode 33.12 HSMCI Transfer Done Timings 33.12.1 Definition 33.12.2 Read Access 33.12.3 Write Access 33.13 Register Write Protection 33.14 High Speed MultiMedia Card Interface (HSMCI) User Interface 33.14.1 HSMCI Control Register 33.14.2 HSMCI Mode Register 33.14.3 HSMCI Data Timeout Register 33.14.4 HSMCI SDCard/SDIO Register 33.14.5 HSMCI Argument Register 33.14.6 HSMCI Command Register 33.14.7 HSMCI Block Register 33.14.8 HSMCI Completion Signal Timeout Register 33.14.9 HSMCI Response Register 33.14.10 HSMCI Receive Data Register 33.14.11 HSMCI Transmit Data Register 33.14.12 HSMCI Status Register 33.14.13 HSMCI Interrupt Enable Register 33.14.14 HSMCI Interrupt Disable Register 33.14.15 HSMCI Interrupt Mask Register 33.14.16 HSMCI DMA Configuration Register 33.14.17 HSMCI Configuration Register 33.14.18 HSMCI Write Protection Mode Register 33.14.19 HSMCI Write Protection Status Register 33.14.20 HSMCI FIFOx Memory Aperture 34. Serial Peripheral Interface (SPI) 34.1 Description 34.2 Embedded Characteristics 34.3 Block Diagram 34.4 Application Block Diagram 34.5 Signal Description 34.6 Product Dependencies 34.6.1 I/O Lines 34.6.2 Power Management 34.6.3 Interrupt 34.6.4 Direct Memory Access Controller (DMAC) 34.7 Functional Description 34.7.1 Modes of Operation 34.7.2 Data Transfer 34.7.3 Master Mode Operations 34.7.3.1 Master Mode Block Diagram 34.7.3.2 Master Mode Flow Diagram 34.7.3.3 Clock Generation 34.7.3.4 Transfer Delays 34.7.3.5 Peripheral Selection 34.7.3.6 SPI Direct Access Memory Controller (DMAC) 34.7.3.7 Peripheral Chip Select Decoding 34.7.3.8 Peripheral Deselection without DMA 34.7.3.9 Peripheral Deselection with DMA 34.7.3.10 Mode Fault Detection 34.7.4 SPI Slave Mode 34.7.5 Register Write Protection 34.8 Serial Peripheral Interface (SPI) User Interface 34.8.1 SPI Control Register 34.8.2 SPI Mode Register 34.8.3 SPI Receive Data Register 34.8.4 SPI Transmit Data Register 34.8.5 SPI Status Register 34.8.6 SPI Interrupt Enable Register 34.8.7 SPI Interrupt Disable Register 34.8.8 SPI Interrupt Mask Register 34.8.9 SPI Chip Select Register 34.8.10 SPI Write Protection Mode Register 34.8.11 SPI Write Protection Status Register 35. Timer Counter (TC) 35.1 Description 35.2 Embedded Characteristics 35.3 Block Diagram 35.4 Pin List 35.5 Product Dependencies 35.5.1 I/O Lines 35.5.2 Power Management 35.5.3 Interrupt Sources 35.6 Functional Description 35.6.1 Description 35.6.2 32-bit Counter 35.6.3 Clock Selection 35.6.4 Clock Control 35.6.5 Operating Modes 35.6.6 Trigger 35.6.7 Capture Mode 35.6.8 Capture Registers A and B 35.6.9 Trigger Conditions 35.6.10 Waveform Mode 35.6.11 Waveform Selection 35.6.11.1 WAVSEL = 00 35.6.11.2 WAVSEL = 10 35.6.11.3 WAVSEL = 01 35.6.11.4 WAVSEL = 11 35.6.12 External Event/Trigger Conditions 35.6.13 Output Controller 35.6.14 2-bit Gray Up/Down Counter for Stepper Motor 35.6.15 Register Write Protection 35.7 Timer Counter (TC) User Interface 35.7.1 TC Channel Control Register 35.7.2 TC Channel Mode Register: Capture Mode 35.7.3 TC Channel Mode Register: Waveform Mode 35.7.4 TC Stepper Motor Mode Register 35.7.5 TC Counter Value Register 35.7.6 TC Register A 35.7.7 TC Register B 35.7.8 TC Register C 35.7.9 TC Status Register 35.7.10 TC Interrupt Enable Register 35.7.11 TC Interrupt Disable Register 35.7.12 TC Interrupt Mask Register 35.7.13 TC Block Control Register 35.7.14 TC Block Mode Register 35.7.15 TC Write Protection Mode Register 36. Pulse Width Modulation Controller (PWM) 36.1 Description 36.2 Embedded characteristics 36.3 Block Diagram 36.4 I/O Lines Description 36.5 Product Dependencies 36.5.1 I/O Lines 36.5.2 Power Management 36.5.3 Interrupt Sources 36.6 Functional Description 36.6.1 PWM Clock Generator 36.6.2 PWM Channel 36.6.2.1 Block Diagram 36.6.2.2 Waveform Properties 36.6.3 PWM Controller Operations 36.6.3.1 Initialization 36.6.3.2 Source Clock Selection Criteria 36.6.3.3 Changing the Duty Cycle or the Period 36.7 Pulse Width Modulation Controller (PWM) User Interface 36.7.1 PWM Mode Register 36.7.2 PWM Enable Register 36.7.3 PWM Disable Register 36.7.4 PWM Status Register 36.7.5 PWM Interrupt Enable Register 36.7.6 PWM Interrupt Disable Register 36.7.7 PWM Interrupt Mask Register 36.7.8 PWM Interrupt Status Register 36.7.9 PWM Channel Mode Register 36.7.10 PWM Channel Duty Cycle Register 36.7.11 PWM Channel Period Register 36.7.12 PWM Channel Counter Register 36.7.13 PWM Channel Update Register 37. Two-wire Interface (TWI) 37.1 Description 37.2 Embedded Characteristics 37.3 List of Abbreviations 37.4 Block Diagram 37.5 I/O Lines Description 37.6 Product Dependencies 37.6.1 I/O Lines 37.6.2 Power Management 37.6.3 Interrupt Sources 37.7 Functional Description 37.7.1 Transfer Format 37.7.2 Modes of Operation 37.7.3 Master Mode 37.7.3.1 Definition 37.7.3.2 Programming Master Mode 37.7.3.3 Master Transmitter Mode 37.7.3.4 Master Receiver Mode 37.7.3.5 Internal Address 37.7.3.6 Using the DMA Controller 37.7.3.7 Read/Write Flowcharts 37.7.4 Multi-master Mode 37.7.4.1 Definition 37.7.4.2 Two Multi-master Modes 37.7.5 Slave Mode 37.7.5.1 Definition 37.7.5.2 Programming Slave Mode 37.7.5.3 Receiving Data 37.7.5.4 Data Transfer Clock Stretching in Read Mode Clock Synchronization in Write Mode Reversal of Read to Write Reversal of Write to Read 37.7.5.5 Using the DMA Controller 37.7.5.6 Read Write Flowcharts 37.7.6 Register Write Protection 37.8 Two-wire Interface (TWI) User Interface 37.8.1 TWI Control Register 37.8.2 TWI Master Mode Register 37.8.3 TWI Slave Mode Register 37.8.4 TWI Internal Address Register 37.8.5 TWI Clock Waveform Generator Register 37.8.6 TWI Status Register 37.8.7 TWI Interrupt Enable Register 37.8.8 TWI Interrupt Disable Register 37.8.9 TWI Interrupt Mask Register 37.8.10 TWI Receive Holding Register 37.8.11 TWI Transmit Holding Register 37.8.12 TWI Write Protection Mode Register 37.8.13 TWI Write Protection Status Register 38. Universal Synchronous Asynchronous Receiver Transmitter (USART) 38.1 Description 38.2 Embedded Characteristics 38.3 Block Diagram 38.4 I/O Lines Description 38.5 Product Dependencies 38.5.1 I/O Lines 38.5.2 Power Management 38.5.3 Interrupt Sources 38.6 Functional Description 38.6.1 Baud Rate Generator 38.6.1.1 Baud Rate in Asynchronous Mode 38.6.1.2 Fractional Baud Rate in Asynchronous Mode 38.6.1.3 Baud Rate in Synchronous Mode or SPI Mode 38.6.1.4 Baud Rate in ISO 7816 Mode 38.6.3 Synchronous and Asynchronous Modes 38.6.3.2 Manchester Encoder 38.6.3.3 Asynchronous Receiver 38.6.3.4 Manchester Decoder 38.6.3.5 Radio Interface: Manchester Encoded USART Application 38.6.3.6 Synchronous Receiver 38.6.3.7 Receiver Operations 38.6.3.8 Parity 38.6.3.9 Multidrop Mode 38.6.3.10 Transmitter Timeguard 38.6.3.11 Receiver Time-out 38.6.3.12 Framing Error 38.6.3.13 Transmit Break 38.6.3.14 Receive Break 38.6.3.15 Hardware Handshaking 38.6.4 ISO7816 Mode 38.6.4.1 ISO7816 Mode Overview 38.6.4.2 Protocol T = 0 38.6.4.3 Protocol T = 1 38.6.5 IrDA Mode 38.6.5.1 IrDA Modulation 38.6.5.2 IrDA Baud Rate 38.6.5.3 IrDA Demodulator 38.6.6 RS485 Mode 38.6.7 SPI Mode 38.6.7.1 Modes of Operation 38.6.7.2 Baud Rate 38.6.7.3 Data Transfer 38.6.7.4 Receiver and Transmitter Control 38.6.7.5 Character Transmission 38.6.7.6 Character Reception 38.6.7.7 Receiver Timeout 38.6.8 LIN Mode 38.6.8.1 Modes of Operation 38.6.8.2 Baud Rate Configuration 38.6.8.3 Receiver and Transmitter Control 38.6.8.4 Character Transmission 38.6.8.5 Character Reception 38.6.8.6 Header Transmission (Master Node Configuration) 38.6.8.7 Header Reception (Slave Node Configuration) 38.6.8.8 Slave Node Synchronization 38.6.8.9 Identifier Parity 38.6.8.10 Node Action 38.6.8.11 Response Data Length 38.6.8.12 Checksum 38.6.8.13 Frame Slot Mode 38.6.8.14 LIN Errors 38.6.8.15 LIN Frame Handling 38.6.8.16 LIN Frame Handling with the DMAC 38.6.8.17 Wake-up Request 38.6.8.18 Bus Idle Time-out 38.6.9 Test Modes 38.6.9.1 Normal Mode 38.6.9.2 Automatic Echo Mode 38.6.9.3 Local Loopback Mode 38.6.9.4 Remote Loopback Mode 38.6.10 Register Write Protection 38.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface 38.7.1 USART Control Register 38.7.2 USART Control Register (SPI_MODE) 38.7.3 USART Mode Register 38.7.4 USART Mode Register (SPI_MODE) 38.7.5 USART Interrupt Enable Register 38.7.6 USART Interrupt Enable Register (SPI_MODE) 38.7.7 USART Interrupt Enable Register (LIN_MODE) 38.7.8 USART Interrupt Disable Register 38.7.9 USART Interrupt Disable Register (SPI_MODE) 38.7.10 USART Interrupt Disable Register (LIN_MODE) 38.7.11 USART Interrupt Mask Register 38.7.12 USART Interrupt Mask Register (SPI_MODE) 38.7.13 USART Interrupt Mask Register (LIN_MODE) 38.7.14 USART Channel Status Register 38.7.15 USART Channel Status Register (SPI_MODE) 38.7.16 USART Channel Status Register (LIN_MODE) 38.7.17 USART Receive Holding Register 38.7.18 USART Transmit Holding Register 38.7.19 USART Baud Rate Generator Register 38.7.20 USART Receiver Time-out Register 38.7.21 USART Transmitter Timeguard Register 38.7.22 USART FI DI RATIO Register 38.7.23 USART Number of Errors Register 38.7.24 USART IrDA Filter Register 38.7.25 USART Manchester Configuration Register 38.7.26 USART LIN Mode Register 38.7.27 USART LIN Identifier Register 38.7.28 USART LIN Baud Rate Register 38.7.29 USART Write Protection Mode Register 38.7.30 USART Write Protection Status Register 39. Universal Asynchronous Receiver Transmitter (UART) 39.1 Description 39.2 Embedded Characteristics 39.3 Block Diagram 39.4 Product Dependencies 39.4.1 I/O Lines 39.4.2 Power Management 39.4.3 Interrupt Sources 39.5 Functional Description 39.5.1 Baud Rate Generator 39.5.2 Receiver 39.5.2.1 Receiver Reset, Enable and Disable 39.5.2.2 Start Detection and Data Sampling 39.5.2.3 Receiver Ready 39.5.2.4 Receiver Overrun 39.5.2.5 Parity Error 39.5.2.6 Receiver Framing Error 39.5.3 Transmitter 39.5.3.1 Transmitter Reset, Enable and Disable 39.5.3.2 Transmit Format 39.5.3.3 Transmitter Control 39.5.4 DMA Support 39.5.5 Test Modes 39.6 Universal Asynchronous Receiver Transmitter (UART) User Interface 39.6.1 UART Control Register 39.6.2 UART Mode Register 39.6.3 UART Interrupt Enable Register 39.6.4 UART Interrupt Disable Register 39.6.5 UART Interrupt Mask Register 39.6.6 UART Status Register 39.6.7 UART Receiver Holding Register 39.6.8 UART Transmit Holding Register 39.6.9 UART Baud Rate Generator Register 40. Controller Area Network (CAN) 40.1 Description 40.2 Embedded Characteristics 40.3 Block Diagram 40.4 Application Block Diagram 40.5 I/O Lines Description 40.6 Product Dependencies 40.6.1 I/O Lines 40.6.2 Power Management 40.6.3 Interrupt Sources 40.7 CAN Controller Features 40.7.1 CAN Protocol Overview 40.7.2 Mailbox Organization 40.7.2.1 Message Acceptance Procedure 40.7.2.2 Receive Mailbox 40.7.2.3 Transmit Mailbox 40.7.3 Time Management Unit 40.7.4 CAN 2.0 Standard Features 40.7.4.1 CAN Bit Timing Configuration 40.7.4.2 Error Detection 40.7.4.3 Overload 40.7.5 Low-power Mode 40.7.5.1 Enabling Low-power Mode 40.7.5.2 Disabling Low-power Mode 40.8 Functional Description 40.8.1 CAN Controller Initialization 40.8.2 CAN Controller Interrupt Handling 40.8.3 CAN Controller Message Handling 40.8.3.1 Receive Handling 40.8.3.2 Transmission Handling 40.8.3.3 Remote Frame Handling 40.8.4 CAN Controller Timing Modes 40.8.4.1 Timestamping Mode 40.8.4.2 Time Triggered Mode 40.8.5 Register Write Protection 40.9 Controller Area Network (CAN) User Interface 40.9.1 CAN Mode Register 40.9.2 CAN Interrupt Enable Register 40.9.3 CAN Interrupt Disable Register 40.9.4 CAN Interrupt Mask Register 40.9.5 CAN Status Register 40.9.6 CAN Baudrate Register 40.9.7 CAN Timer Register 40.9.8 CAN Timestamp Register 40.9.9 CAN Error Counter Register 40.9.10 CAN Transfer Command Register 40.9.11 CAN Abort Command Register 40.9.12 CAN Write Protection Mode Register 40.9.13 CAN Write Protection Status Register 40.9.14 CAN Message Mode Register 40.9.15 CAN Message Acceptance Mask Register 40.9.16 CAN Message ID Register 40.9.17 CAN Message Family ID Register 40.9.18 CAN Message Status Register 40.9.19 CAN Message Data Low Register 40.9.20 CAN Message Data High Register 40.9.21 CAN Message Control Register 41. Analog-to-Digital Converter (ADC) 41.1 Description 41.2 Embedded Characteristics 41.3 Block Diagram 41.4 Signal Description 41.5 Product Dependencies 41.5.1 Power Management 41.5.2 Interrupt Sources 41.5.3 I/O Lines 41.5.4 Timer Triggers 41.5.5 Conversion Performances 41.6 Functional Description 41.6.1 Analog-to-Digital Conversion 41.6.2 ADC Clock 41.6.3 ADC Reference Voltage 41.6.4 Conversion Resolution 41.6.5 Conversion Results 41.6.6 Conversion Triggers 41.6.7 Sleep Mode and Conversion Sequencer 41.6.8 Comparison Window 41.6.9 ADC Timings 41.6.10 Touchscreen 41.6.10.1 Touchscreen Mode 41.6.10.2 4-wire Resistive Touchscreen Principles 41.6.10.3 4-wire Position Measurement Method 41.6.10.4 4-wire Pressure Measurement Method 41.6.10.5 5-wire Resistive Touchscreen Principles 41.6.10.6 5-wire Position Measurement Method 41.6.10.7 Sequence and Noise Filtering 41.6.10.8 Measured Values, Registers and Flags 41.6.10.9 Pen Detect Method 41.6.11 Buffer Structure 41.6.11.1 Classical ADC Channels Only 41.6.11.2 Touchscreen Channels Only 41.6.11.3 Interleaved Channels 41.6.11.4 Pen Detection Status 41.6.12 Register Write Protection 41.7 Analog-to-Digital (ADC) User Interface 41.7.1 ADC Control Register 41.7.2 ADC Mode Register 41.7.3 ADC Channel Sequence 1 Register 41.7.4 ADC Channel Enable Register 41.7.5 ADC Channel Disable Register 41.7.6 ADC Channel Status Register 41.7.7 ADC Last Converted Data Register 41.7.8 ADC Interrupt Enable Register 41.7.9 ADC Interrupt Disable Register 41.7.10 ADC Interrupt Mask Register 41.7.11 ADC Interrupt Status Register 41.7.12 ADC Overrun Status Register 41.7.13 ADC Extended Mode Register 41.7.14 ADC Compare Window Register 41.7.15 ADC Channel Data Register 41.7.16 ADC Analog Control Register 41.7.17 ADC Touchscreen Mode Register 41.7.18 ADC Touchscreen X Position Register 41.7.19 ADC Touchscreen Y Position Register 41.7.20 ADC Touchscreen Pressure Register 41.7.21 ADC Trigger Register 41.7.22 ADC Write Protection Mode Register 41.7.23 ADC Write Protection Status Register 42. Software Modem Device (SMD) 42.1 Description 42.2 Embedded Characteristics 42.3 Block Diagram 42.4 Software Modem Device (SMD) User Interface 42.4.1 SMD Drive Register 43. Synchronous Serial Controller (SSC) 43.1 Description 43.2 Embedded Characteristics 43.6 Pin Name List 43.7 Product Dependencies 43.7.1 I/O Lines 43.7.2 Power Management 43.7.3 Interrupt 43.8 Functional Description 43.8.1 Clock Management 43.8.1.2 Transmitter Clock Management 43.8.1.3 Receiver Clock Management 43.8.1.4 Serial Clock Ratio Considerations 43.8.2 Transmitter Operations 43.8.7 Data Format 43.8.8 Loop Mode 43.8.9 Interrupt 43.8.10 Register Write Protection 43.9 Synchronous Serial Controller (SSC) User Interface 43.9.1 SSC Control Register 43.9.2 SSC Clock Mode Register 43.9.3 SSC Receive Clock Mode Register 43.9.4 SSC Receive Frame Mode Register 43.9.5 SSC Transmit Clock Mode Register 43.9.6 SSC Transmit Frame Mode Register 43.9.7 SSC Receive Holding Register 43.9.8 SSC Transmit Holding Register 43.9.9 SSC Receive Synchronization Holding Register 43.9.10 SSC Transmit Synchronization Holding Register 43.9.11 SSC Receive Compare 0 Register 43.9.12 SSC Receive Compare 1 Register 43.9.13 SSC Status Register 43.9.14 SSC Interrupt Enable Register 43.9.15 SSC Interrupt Disable Register 43.9.16 SSC Interrupt Mask Register 43.9.17 SSC Write Protection Mode Register 43.9.18 SSC Write Protection Status Register 44. Ethernet 10/100 MAC (EMAC) 44.1 Description 44.2 Embedded Characteristics 44.4 Functional Description 44.4.1 Clock 44.4.2 Memory Interface 44.4.2.1 FIFO 44.4.2.2 Receive Buffers 44.4.2.3 Transmit Buffer 44.4.3 Transmit Block 44.4.4 Pause Frame Support 44.4.5 Receive Block 44.4.6 Address Checking Block 44.4.7 Broadcast Address 44.4.8 Hash Addressing 44.4.9 Copy All Frames (or Promiscuous Mode) 44.4.10 Type ID Checking 44.4.11 VLAN Support 44.4.12 PHY Maintenance 44.4.13 Physical Interface 44.4.13.1 RMII Transmit and Receive Operation 44.5 Programming Interface 44.5.1 Initialization 44.5.1.4 Address Matching 44.5.1.5 Interrupts 44.5.1.6 Transmitting Frames 44.5.1.7 Receiving Frames 44.6 Ethernet MAC 10/100 (EMAC) User Interface 44.6.1 Network Control Register 44.6.2 Network Configuration Register 44.6.3 Network Status Register 44.6.4 Transmit Status Register 44.6.5 Receive Buffer Queue Pointer Register 44.6.6 Transmit Buffer Queue Pointer Register 44.6.7 Receive Status Register 44.6.8 Interrupt Status Register 44.6.9 Interrupt Enable Register 44.6.10 Interrupt Disable Register 44.6.11 Interrupt Mask Register 44.6.12 PHY Maintenance Register 44.6.13 Pause Time Register 44.6.14 Hash Register Bottom 44.6.15 Hash Register Top 44.6.16 Specific Address 1 Bottom Register 44.6.17 Specific Address 1 Top Register 44.6.18 Specific Address 2 Bottom Register 44.6.19 Specific Address 2 Top Register 44.6.20 Specific Address 3 Bottom Register 44.6.21 Specific Address 3 Top Register 44.6.22 Specific Address 4 Bottom Register 44.6.23 Specific Address 4 Top Register 44.6.24 Type ID Checking Register 44.6.25 User Input/Output Register 44.6.26 EMAC Statistics Registers 44.6.26.1 Pause Frames Received Register 44.6.26.2 Frames Transmitted OK Register 44.6.26.3 Single Collision Frames Register 44.6.26.4 Multicollision Frames Register 44.6.26.5 Frames Received OK Register 44.6.26.6 Frames Check Sequence Errors Register 44.6.26.7 Alignment Errors Register 44.6.26.8 Deferred Transmission Frames Register 44.6.26.9 Late Collisions Register 44.6.26.10 Excessive Collisions Register 44.6.26.11 Transmit Underrun Errors Register 44.6.26.12 Carrier Sense Errors Register 44.6.26.13 Receive Resource Errors Register 44.6.26.14 Receive Overrun Errors Register 44.6.26.15 Receive Symbol Errors Register 44.6.26.16 Excessive Length Errors Register 44.6.26.17 Receive Jabbers Register 44.6.26.18 Undersize Frames Register 44.6.26.19 SQE Test Errors Register 44.6.26.20 Received Length Field Mismatch Register 45. LCD Controller (LCDC) 45.1 Description 45.2 Embedded Characteristics 45.3 Block Diagram 45.4 I/O Lines Description 45.5 Product Dependencies 45.5.1 I/O Lines 45.5.2 Power Management 45.5.3 Interrupt Sources 45.6 Functional Description 45.6.1 Timing Engine Configuration 45.6.1.1 Pixel Clock Period Configuration 45.6.1.2 Horizontal and Vertical Synchronization Configuration 45.6.1.3 Timing Engine Power Up Software Operation 45.6.1.4 Timing Engine Power Down Software Operation 45.6.2 DMA Software Operations 45.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure 45.6.2.2 Programming a DMA Channel 45.6.2.3 Disabling a DMA channel 45.6.2.4 DMA Dynamic Linking of a New Transfer Descriptor 45.6.2.5 DMA Interrupt Generation 45.6.2.6 DMA Address Alignment Requirements 45.6.3 Display Software Configuration 45.6.3.1 System Bus Access Attributes 45.6.3.2 Color Attributes 45.6.3.3 Window Position, Size, Scaling and Striding Attributes 45.6.3.4 Overlay Blender Attributes 45.6.3.5 Window Attributes Software Operation 45.6.4 RGB Frame Buffer Memory Bitmap 45.6.4.1 1 bpp Through Color Lookup Table 45.6.4.2 2 bpp Through Color Lookup Table 45.6.4.3 4 bpp Through Color Lookup Table 45.6.4.4 8 bpp Through Color Lookup Table 45.6.4.5 12 bpp Memory Mapping, RGB 4:4:4 45.6.4.6 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4 45.6.4.7 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4 45.6.4.8 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5 45.6.4.9 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5 45.6.4.10 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:6 45.6.4.11 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6 45.6.4.12 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:6 45.6.4.13 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6 45.6.4.14 24 bpp Unpacked Memory Mapping, RGB 8:8:8 45.6.4.15 24 bpp Packed Memory Mapping, RGB 8:8:8 45.6.4.16 25 bpp Memory Mapping, ARGB 1:8:8:8 45.6.4.17 32 bpp Memory Mapping, ARGB 8:8:8:8 45.6.4.18 32 bpp Memory Mapping, RGBA 8:8:8:8 45.6.5 YUV Frame Buffer Memory Mapping 45.6.5.1 AYCbCr 4:4:4 Interleaved Frame Buffer Memory Mapping 45.6.5.2 4:2:2 Interleaved Mode Frame Buffer Memory Mapping 45.6.5.3 4:2:2 Semiplanar Mode Frame Buffer Memory Mapping 45.6.5.4 4:2:2 Planar Mode Frame Buffer Memory Mapping 45.6.5.5 4:2:0 Planar Mode Frame Buffer Memory Mapping 45.6.5.6 4:2:0 Semiplanar Frame Buffer memory Mapping 45.6.6 Chrominance Upsampling Unit 45.6.6.1 Chrominance Upsampling Algorithm 45.6.7 Line and Pixel Striding 45.6.7.1 Line Striding 45.6.7.2 Pixel Striding 45.6.8 Color Space Conversion Unit 45.6.9 Two Dimension Scaler 45.6.9.1 Horizontal Scaler 45.6.9.2 Vertical Scaler 45.6.10 Hardware Cursor 45.6.11 Color Combine Unit 45.6.11.1 Window Overlay 45.6.11.2 Overlay Blending 45.6.11.3 Global Alpha Blender 45.6.11.4 Window Blending 45.6.11.5 Color Keying 45.6.12 LCDC Overall Performance 45.6.12.1 Color Lookup Table (CLUT) 45.6.12.2 RGB Mode Fetch Performance 45.6.12.3 YUV Mode Fetch Performance 45.6.13 Output Timing Generation 45.6.13.1 Active Display Timing Mode 45.6.14 Output Format 45.6.14.1 Active Mode Output Pin Assignment 45.7 LCD Controller (LCDC) User Interface 45.7.1 LCD Controller Configuration Register 0 45.7.2 LCD Controller Configuration Register 1 45.7.3 LCD Controller Configuration Register 2 45.7.4 LCD Controller Configuration Register 3 45.7.5 LCD Controller Configuration Register 4 45.7.6 LCD Controller Configuration Register 5 45.7.7 LCD Controller Configuration Register 6 45.7.8 LCD Controller Enable Register 45.7.9 LCD Controller Disable Register 45.7.10 LCD Controller Status Register 45.7.11 LCD Controller Interrupt Enable Register 45.7.12 LCD Controller Interrupt Disable Register 45.7.13 LCD Controller Interrupt Mask Register 45.7.14 LCD Controller Interrupt Status Register 45.7.15 Base Layer Channel Enable Register 45.7.16 Base Layer Channel Disable Register 45.7.17 Base Layer Channel Status Register 45.7.18 Base Layer Interrupt Enable Register 45.7.19 Base Layer Interrupt Disable Register 45.7.20 Base Layer Interrupt Mask Register 45.7.21 Base Layer Interrupt Status Register 45.7.22 Base Layer Head Register 45.7.23 Base Layer Address Register 45.7.24 Base Layer Control Register 45.7.25 Base Layer Next Register 45.7.26 Base Layer Configuration 0 Register 45.7.27 Base Layer Configuration 1 Register 45.7.28 Base Layer Configuration 2 Register 45.7.29 Base Layer Configuration 3 Register 45.7.30 Base Layer Configuration 4 Register 45.7.31 Overlay 1 Layer Channel Enable Register 45.7.32 Overlay 1 Layer Channel Disable Register 45.7.33 Overlay 1 Layer Channel Status Register 45.7.34 Overlay 1 Layer Interrupt Enable Register 45.7.35 Overlay 1 Layer Interrupt Disable Register 45.7.36 Overlay 1 Layer Interrupt Mask Register 45.7.37 Overlay 1 Layer Interrupt Status Register 45.7.38 Overlay 1 Layer Head Register 45.7.39 Overlay 1 Layer Address Register 45.7.40 Overlay 1 Layer Control Register 45.7.41 Overlay 1 Layer Next Register 45.7.42 Overlay 1 Layer Configuration 0 Register 45.7.43 Overlay 1 Layer Configuration 1 Register 45.7.44 Overlay 1 Layer Configuration 2 Register 45.7.45 Overlay 1 Layer Configuration 3 Register 45.7.46 Overlay 1 Layer Configuration 4 Register 45.7.47 Overlay 1 Layer Configuration 5 Register 45.7.48 Overlay 1 Layer Configuration 6 Register 45.7.49 Overlay 1 Layer Configuration 7 Register 45.7.50 Overlay 1 Layer Configuration 8 Register 45.7.51 Overlay1 Layer Configuration 9 Register 45.7.52 High End Overlay Layer Channel Enable Register 45.7.53 High End Overlay Layer Channel Disable Register 45.7.54 High End Overlay Layer Channel Status Register 45.7.55 High End Overlay Layer Interrupt Enable Register 45.7.56 High End Overlay Layer Interrupt Disable Register 45.7.57 High End Overlay Layer Interrupt Mask Register 45.7.58 High End Overlay Layer Interrupt Status Register 45.7.59 High End Overlay Layer Head Register 45.7.60 High End Overlay Layer Address Register 45.7.61 High End Overlay Layer Control Register 45.7.62 High End Overlay Layer Next Register 45.7.63 High End Overlay Layer U-UV Head Register 45.7.64 High End Overlay Layer U-UV Address Register 45.7.65 High End Overlay Layer U-UV Control Register 45.7.66 High End Overlay Layer U-UV Next Register 45.7.67 High End Overlay Layer V Head Register 45.7.68 High End Overlay Layer V Address Register 45.7.69 High End Overlay Layer V Control Register 45.7.70 High End Overlay Layer V Next Register 45.7.71 High End Overlay Layer Configuration 0 Register 45.7.72 High End Overlay Layer Configuration 1 Register 45.7.73 High End Overlay Layer Configuration 2 Register 45.7.74 High End Overlay Layer Configuration 3 Register 45.7.75 High End Overlay Layer Configuration 4 Register 45.7.76 High End Overlay Layer Configuration 5 Register 45.7.77 High End Overlay Layer Configuration 6 Register 45.7.78 High End Overlay Layer Configuration 7 Register 45.7.79 High End Overlay Layer Configuration 8 Register 45.7.80 High End Overlay Layer Configuration 9 Register 45.7.81 High End Overlay Layer Configuration 10 Register 45.7.82 High End Overlay Layer Configuration 11 Register 45.7.83 High End Overlay Layer Configuration 12 Register 45.7.84 High End Overlay Layer Configuration 13 Register 45.7.85 High End Overlay Layer Configuration 14 Register 45.7.86 High End Overlay Layer Configuration 15 Register 45.7.87 High End Overlay Layer Configuration 16 Register 45.7.88 Hardware Cursor Layer Channel Enable Register 45.7.89 Hardware Cursor Layer Channel Disable Register 45.7.90 Hardware Cursor Layer Channel Status Register 45.7.91 Hardware Cursor Layer Interrupt Enable Register 45.7.92 Hardware Cursor Layer Interrupt Disable Register 45.7.93 Hardware Cursor Layer Interrupt Mask Register 45.7.94 Hardware Cursor Layer Interrupt Status Register 45.7.95 Hardware Cursor Layer Head Register 45.7.96 Hardware Cursor Layer Address Register 45.7.97 Hardware Cursor Layer Control Register 45.7.98 Hardware Cursor Layer Next Register 45.7.99 Hardware Cursor Layer Configuration 0 Register 45.7.100 Hardware Cursor Layer Configuration 1 Register 45.7.101 Hardware Cursor Layer Configuration 2 Register 45.7.102 Hardware Cursor Layer Configuration 3 Register 45.7.103 Hardware Cursor Layer Configuration 4 Register 45.7.104 Hardware Cursor Layer Configuration 6 Register 45.7.105 Hardware Cursor Layer Configuration 7 Register 45.7.106 Hardware Cursor Layer Configuration 8 Register 45.7.107 Hardware Cursor Layer Configuration 9 Register 45.7.108 Base CLUT Register x Register 45.7.109 Overlay 1 CLUT Register x Register 45.7.110 High End Overlay CLUT Register x Register 45.7.111 Hardware Cursor CLUT Register x Register 46. Electrical Characteristics 46.1 Absolute Maximum Ratings 46.2 DC Characteristics 46.3 Power Consumption 46.3.1 Power Consumption versus Modes 46.4 Clock Characteristics 46.4.1 Processor Clock Characteristics 46.4.2 Master Clock Characteristics 46.5 Main Oscillator Characteristics 46.5.1 Crystal Oscillator Characteristics 46.5.2 XIN Clock Characteristics 46.6 12 MHz RC Oscillator Characteristics 46.7 32 kHz Oscillator Characteristics 46.7.1 32 kHz Crystal Characteristics 46.7.2 XIN32 Clock Characteristics 46.8 32 kHz RC Oscillator Characteristics 46.9 PLL Characteristics 46.9.1 UTMI PLL Characteristics 46.10 I/Os 46.11 USB HS Characteristics 46.12 USB Transceiver Characteristics 46.13 Analog-to-Digital Converter (ADC) 46.14 POR Characteristics 46.14.1 Core Power Supply POR Characteristics 46.14.2 Backup Power Supply POR Characteristics 46.15 Power Sequence Requirements 46.15.1 Power-Up Sequence 46.15.2 Power-Down Sequence 46.16 SMC Timings 46.16.1 Timing Conditions 46.16.2 Timing Extraction 46.16.2.1 Zero Hold Mode Restrictions 46.16.2.2 Read Timings 46.16.2.3 Write Timings 46.17 DDRSDRC Timings 46.18 Peripheral Timings 46.18.1 SPI 46.18.1.1 Maximum SPI Frequency Master Write Mode Master Read Mode Slave Read Mode Slave Write Mode 46.18.1.2 Timing Conditions 46.18.1.3 Timing Extraction 46.18.2 SSC 46.18.2.1 Timing Conditions 46.18.2.2 Timing Extraction 46.18.3 HSMCI 46.18.4 EMAC 46.18.4.1 Timing Conditions 46.18.4.2 Timing Constraints 46.18.4.3 RMII Mode 46.18.5 USART in SPI Mode Timings 46.18.5.1 Timing conditions 46.18.5.2 Timing extraction 46.19 Two-wire Interface Characteristics 47. Mechanical Overview 47.1 217-ball BGA Package 48. Marking 49. Ordering Information 50. Errata 50.1 External Bus Interface (EBI) 50.1.1 EBI: Data lines are Hi-Z after reset 50.2 Reset Controller (RSTC) 50.2.1 RSTC: Reset during SDRAM Accesses 50.3 Static Memory Controller (SMC) 50.3.1 SMC: SMC DELAY I/O registers are write-only 50.4 USB High Speed Host Port (UHPHS) and Device Port (UDPHS) 50.4.1 UHPHS/UDPHS: Bad Lock of the USB High speed transceiver DLL 50.5 Timer Counter (TC) 50.5.1 TC: The TIOA5 signal is not well connected 50.6 LCD Controller (LCDC) 50.6.1 LCDC: LCDC PWM is not usable 50.7 Boot Strategy 50.7.1 NAND Flash Boot Detection using ONFI parameters does not work 50.8 Real Time Clock (RTC) 50.8.1 RTC: Interrupt Mask Register cannot be used Revision History Table of Contents