Datasheet dsPIC33CH128MP508 (Microchip) - 2

dsPIC33CH128MP508 FAMILY Advanced Analog Features Other Features
• Four ADC Modules: • PPS to Allow Function Remap - One module for Master core • Programmable Cyclic Redundancy Check (CRC) - Three modules for Slave core for the Master - 12-bit, 3.5 Msps ADC • Two SENT Modules for the Master - Up to 18 conversion channels • Four DAC/Analog Comparator Modules:
Direct Memory Access (DMA)
- One module for Master core • Eight DMA Channels: - Three modules for Slave core - Six DMA channels available for the Master core - 12-bit DACs with hardware slope - Two DMA channels available for the Slave core compensation - 15 ns analog comparators
Debugger Development Support
• Three PGA Modules: • In-Circuit and In-Application Programming - Three modules for Slave core • Simultaneous Debugging Support for Master and - Can be read by Master ADC Slave Cores - Option to interface with Master ADC • Master Only Debug and Slave Only Debug • Shared DAC/Analog Output: Support - DAC/analog comparator outputs • Master with Three Complex, Five Simple - PGA outputs Breakpoints and Slave with One Complex, Two Simple Breakpoints
Communication Interfaces
• IEEE 1149.2 Compatible (JTAG) Boundary Scan • Three UART Modules: • Trace Buffer and Run-Time Watch - Two modules for Master core
Safety Features
- One module for Slave core - Support for DMX and LIN/J2602 protocols • DMT (Deadman Timer) • Three 4-Wire SPI/I2S Modules: • ECC (Error Correcting Code) - Two modules for Master core • WDT (Watchdog Timer) - One module for Slave core • CodeGuard™ Security • CAN Flexible Data-Rate (FD) Module for the • CRC (Cyclic Redundancy Check) Master Core • Two-Speed Start-up • Three I2C Modules: • Fail-Safe Clock Monitoring - Two modules for Master • Backup FRC (BFRC) - One module for Slave • Capless Internal Voltage Regulator - Support for SMBus • Virtual Pins for Redundancy and Monitoring
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1: -40°C to +125°C) Compliant • Class B Safety Library, IEC 60730 DS70005319D-page 2  2017-2019 Microchip Technology Inc. Document Outline Operating Conditions Core: Dual 16-Bit dsPIC33CH CPU Clock Management Power Management High-Resolution PWM with Fine Edge Placement Timers/Output Compare/Input Capture Advanced Analog Features Communication Interfaces Other Features Direct Memory Access (DMA) Debugger Development Support Safety Features Qualification and Class B Support TABLE 1: Master and Slave Core Features dsPIC33CH128MP508 Product Families TABLE 2: dsPIC33CHXXXMP50X Family TABLE 3: dsPIC33CHXXXMP20X Family with No Can FD Pin Diagrams TABLE 4: 28-Pin SSOP Pin Diagrams (Continued) TABLE 5: 28-Pin UQFN Pin Diagrams (Continued) TABLE 6: 36-Pin UQFN Pin Diagrams (Continued) TABLE 7: 48-Pin TQFP/UQFN Pin Diagrams (Continued) TABLE 8: 64-Pin TQFP/QFN Pin Diagrams (Continued) TABLE 9: 80-Pin TQFP Table of Contents Most Current Data Sheet Errata Customer Notification System Referenced Sources 1.0 Device Overview FIGURE 1-1: Slave Core Code Transfer Block Diagram FIGURE 1-2: dsPIC33CH128MP508 Family Block Diagram(1) TABLE 1-1: Pinout I/O Descriptions 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers 2.1 Basic Connection Requirements 2.2 Decoupling Capacitors FIGURE 2-1: Recommended Minimum Connection 2.2.1 Bulk Capacitors 2.3 Master Clear (MCLR) Pin FIGURE 2-2: Example of MCLR Pin Connections 2.4 ICSP Pins 2.5 External Oscillator Pins FIGURE 2-3: Suggested Placement of the Oscillator Circuit 2.6 Oscillator Value Conditions on Device Start-up 2.7 Unused I/Os 2.8 Targeted Applications FIGURE 2-4: Interleaved PFC FIGURE 2-5: Phase-Shifted Full-Bridge Converter FIGURE 2-6: Off-Line UPS 3.0 Master Modules 3.1 Master CPU 3.1.1 Registers 3.1.2 Instruction Set 3.1.3 Data Space Addressing 3.1.4 Addressing Modes FIGURE 3-1: dsPIC33CH128MP508 Family (Master) CPU Block Diagram 3.1.5 Programmer’s Model TABLE 3-1: Programmer’s Model Register Descriptions FIGURE 3-2: Programmer’s Model (Master) 3.1.6 CPU Resources 3.1.7 CPU Control/Status Registers Register 3-1: SR: CPU STATUS Register Register 3-2: CORCON: Core Control Register Register 3-3: CTXTSTAT: CPU W Register Context Status Register 3.1.8 Arithmetic Logic Unit (ALU) 3.1.9 DSP Engine TABLE 3-2: DSP Instructions Summary 3.2 Master Memory Organization 3.2.1 Program Address Space FIGURE 3-3: Program Memory Map for Master dsPIC33CH128MPXXX Devices(1) FIGURE 3-4: Program Memory Map for Master dsPIC33CH64MPXXX Devices(1) FIGURE 3-5: Program Memory Organization 3.2.2 Unique Device Identifier (UDID) TABLE 3-3: UDID Addresses 3.2.3 Data Address Space (Master) FIGURE 3-6: Data Memory Map for dsPIC33CH128MP508 Devices 3.2.4 Memory Resources 3.2.5 SFR Maps TABLE 3-4: Master SFR Block 000h TABLE 3-5: Master SFR Block 100h TABLE 3-6: Master SFR Block 200h TABLE 3-7: Master SFR Block 300h-400h TABLE 3-8: Master SFR Block 500h TABLE 3-9: Master SFR Block 600h TABLE 3-10: Master SFR Block 700h TABLE 3-11: Master SFR Block 800h TABLE 3-12: Master SFR Block 900h TABLE 3-13: Master SFR Block A00h TABLE 3-14: Master SFR Block B00h TABLE 3-15: Master SFR Block C00h TABLE 3-16: Master SFR Block D00h TABLE 3-17: Master SFR Block E00h TABLE 3-18: Master SFR Block F00h FIGURE 3-7: Program Space Visibility (PSV) Read Address Generation FIGURE 3-8: Paged Data Memory Space TABLE 3-19: Overflow and Underflow Scenarios at Page 0 and PSV Space Boundaries(2,3,4) FIGURE 3-9: CALL Stack Frame 3.2.6 Instruction Addressing Modes TABLE 3-20: Fundamental Addressing Modes Supported 3.2.7 Modulo Addressing FIGURE 3-10: Modulo Addressing Operation Example 3.2.8 Bit-Reversed Addressing FIGURE 3-11: Bit-Reversed Addressing Example TABLE 3-21: Bit-Reversed Addressing Sequence (16-Entry) 3.2.9 Interfacing Program and Data Memory Spaces TABLE 3-22: Program Space Address Construction FIGURE 3-12: Data Access from Program Space Address Generation FIGURE 3-13: Accessing Program Memory with Table Instructions 3.3 Master Flash Program Memory 3.3.1 Flash Programming Operations FIGURE 3-14: Addressing for Table Registers 3.3.2 RTSP Operation EXAMPLE 3-1: Flash Write/Read FIGURE 3-15: Uncompressed/ Compressed Format 3.3.3 Error Correcting Code (ECC) 3.3.4 Control Registers 3.3.5 NVM Control Registers Register 3-4: NVMCON: Nonvolatile Memory (NVM) Control Register Register 3-5: NVMADR: Nonvolatile Memory Lower Address Register Register 3-6: NVMADRU: Nonvolatile Memory Upper Address Register Register 3-7: NVMKEY: Nonvolatile Memory Key Register Register 3-8: NVMSRCADRL: NVM Source Data Address Register Low Register 3-9: NVMSRCADRH: NVM Source Data Address Register High 3.3.6 ECC Control Registers Register 3-10: ECCCONL: ECC Fault Injection Configuration Register Low Register 3-11: ECCCONH: ECC Fault Injection Configuration Register High Register 3-12: ECCADDRL: ECC Fault Inject Address Compare Register Low Register 3-13: ECCADDRH: ECC Fault Inject Address Compare Register High Register 3-14: ECCSTATL: ECC System Status Display Register Low Register 3-15: ECCSTATH: ECC System Status Display Register High 3.4 Master Resets FIGURE 3-16: Master Reset System Block Diagram 3.4.1 Reset Resources 3.4.2 Reset Control Register Register 3-16: RCON: Reset Control Register(1) 3.5 Master Interrupt Controller 3.5.1 Interrupt Vector Table 3.5.2 Reset Sequence FIGURE 3-17: dsPIC33CH128MP508 Family Master Interrupt Vector Table FIGURE 3-18: dsPIC33CH128MP508 Alternate Master Interrupt Vector Table TABLE 3-23: Trap Table TABLE 3-24: Master Interrupt Vector Details(1) TABLE 3-25: Master Interrupt Flag Registers TABLE 3-26: Master Interrupt Enable Registers TABLE 3-27: Master Interrupt Priority Registers 3.5.3 Interrupt Resources 3.5.4 Interrupt Control and Status Registers 3.5.5 Interrupt Status/Control Registers Register 3-17: SR: CPU STATUS Register(1) Register 3-18: CORCON: Core Control Register(1) Register 3-19: INTCON1: Interrupt Control Register 1 Register 3-20: INTCON2: Interrupt Control Register 2 Register 3-21: INTCON3: Interrupt Control Register 3 Register 3-22: INTCON4: Interrupt Control Register 4 Register 3-23: INTTREG: Interrupt Control and Status Register 3.6 Master I/O Ports 3.6.1 Parallel I/O (PIO) Ports TABLE 3-28: Pin and ANSELx Availability TABLE 3-29: 5V Input Tolerant Ports FIGURE 3-19: Block Diagram of a Typical Shared Port Structure 3.6.2 Configuring Analog and Digital Port Pins 3.6.3 Master Port Control Registers Register 3-24: ANSELx: Analog Select for PORTx Register Register 3-25: TRISx: Output Enable for PORTx Register Register 3-26: PORTx: Input Data for PORTx Register Register 3-27: LATx: Output Data for PORTx Register Register 3-28: ODCx: Open-Drain Enable for PORTx Register Register 3-29: CNPUx: Change Notification Pull-up Enable for PORTx Register Register 3-30: CNPDx: Change Notification Pull-Down Enable for PORTx Register Register 3-31: CNCONx: Change Notification Control for PORTx Register Register 3-32: CNEN0x: Interrupt Change Notification Enable for PORTx Register Register 3-33: CNSTATx: Interrupt Change Notification Status for PORTx Register Register 3-34: CNEN1x: Interrupt Change Notification Edge Select for PORTx Register Register 3-35: CNFx: Interrupt Change Notification Flag for PORTx Register 3.6.4 Input Change Notification (ICN) TABLE 3-30: Change Notification Event Options 3.6.5 Peripheral Pin Select (PPS) 3.6.6 Available Pins 3.6.7 Available Peripherals 3.6.8 Controlling Configuration Changes 3.6.9 Considerations for Peripheral Pin Selection 3.6.10 Input Mapping FIGURE 3-20: Remappable Input for U1RX EXAMPLE 3-2: Configuring UART1 Input and Output Functions TABLE 3-31: Master Remappable Pin Inputs 3.6.11 Virtual Connections 3.6.12 Slave PPS Inputs to Master Core PPS TABLE 3-32: Selectable Input Sources (Maps Input to Function) 3.6.13 Output Mapping FIGURE 3-21: Multiplexing Remappable Outputs for RPn 3.6.14 Mapping Limitations TABLE 3-33: Master Remappable Output Pin Registers(1) TABLE 3-34: Output Selection for Remappable Pins (RPn)(1) 3.6.15 I/O Helpful Tips 3.6.16 I/O Ports Resources TABLE 3-35: PORTA Register Summary TABLE 3-36: PORTB Register Summary TABLE 3-37: PORTC Register Summary TABLE 3-38: PORTD Register Summary TABLE 3-39: PORTE Register Summary 3.6.17 Peripheral Pin Select Registers Register 3-36: RPCON: Peripheral Remapping Configuration Register(1) Register 3-37: RPINR0: Peripheral Pin Select Input Register Register 3-38: RPINR1: Peripheral Pin Select Input Register 1 Register 3-39: RPINR2: Peripheral Pin Select Input Register 2 Register 3-40: RPINR3: Peripheral Pin Select Input Register 3 Register 3-41: RPINR4: Peripheral Pin Select Input Register 4 Register 3-42: RPINR5: Peripheral Pin Select Input Register 5 Register 3-43: RPINR6: Peripheral Pin Select Input Register 6 Register 3-44: RPINR7: Peripheral Pin Select Input Register 7 Register 3-45: RPINR8: Peripheral Pin Select Input Register 8 Register 3-46: RPINR9: Peripheral Pin Select Input Register 9 Register 3-47: RPINR10: Peripheral Pin Select Input Register 10 Register 3-48: RPINR11: Peripheral Pin Select Input Register 11 Register 3-49: RPINR12: Peripheral Pin Select Input Register 12 Register 3-50: RPINR13: Peripheral Pin Select Input Register 13 Register 3-51: RPINR14: Peripheral Pin Select Input Register 14 Register 3-52: RPINR15: Peripheral Pin Select Input Register 15 Register 3-53: RPINR18: Peripheral Pin Select Input Register 18 Register 3-54: RPINR19: Peripheral Pin Select Input Register 19 Register 3-55: RPINR20: Peripheral Pin Select Input Register 20 Register 3-56: RPINR21: Peripheral Pin Select Input Register 21 Register 3-57: RPINR22: Peripheral Pin Select Input Register 22 Register 3-58: RPINR23: Peripheral Pin Select Input Register 23 Register 3-59: RPINR26: Peripheral Pin Select Input Register 26 Register 3-60: RPINR30: Peripheral Pin Select Input Register 30 Register 3-61: RPINR37: Peripheral Pin Select Input Register 37 Register 3-62: RPINR38: Peripheral Pin Select Input Register 38 Register 3-63: RPINR42: Peripheral Pin Select Input Register 42 Register 3-64: RPINR43: Peripheral Pin Select Input Register 43 Register 3-65: RPINR44: Peripheral Pin Select Input Register 44 Register 3-66: RPINR45: Peripheral Pin Select Input Register 45 Register 3-67: RPINR46: Peripheral Pin Select Input Register 46 Register 3-68: RPINR47: Peripheral Pin Select Input Register 47 Register 3-69: RPOR0: Peripheral Pin Select Output Register 0 Register 3-70: RPOR1: Peripheral Pin Select Output Register 1 Register 3-71: RPOR2: Peripheral Pin Select Output Register 2 Register 3-72: RPOR3: Peripheral Pin Select Output Register 3 Register 3-73: RPOR4: Peripheral Pin Select Output Register 4 Register 3-74: RPOR5: Peripheral Pin Select Output Register 5 Register 3-75: RPOR6: Peripheral Pin Select Output Register 6 Register 3-76: RPOR7: Peripheral Pin Select Output Register 7 Register 3-77: RPOR8: Peripheral Pin Select Output Register 8 Register 3-78: RPOR9: Peripheral Pin Select Output Register 9 Register 3-79: RPOR10: Peripheral Pin Select Output Register 10 Register 3-80: RPOR11: Peripheral Pin Select Output Register 11 Register 3-81: RPOR12: Peripheral Pin Select Output Register 12 Register 3-82: RPOR13: Peripheral Pin Select Output Register 13 Register 3-83: RPOR14: Peripheral Pin Select Output Register 14 Register 3-84: RPOR15: Peripheral Pin Select Output Register 15 Register 3-85: RPOR16: Peripheral Pin Select Output Register 16 Register 3-86: RPOR17: Peripheral Pin Select Output Register 17 Register 3-87: RPOR18: Peripheral Pin Select Output Register 18 Register 3-88: RPOR19: Peripheral Pin Select Output Register 19 Register 3-89: RPOR20: Peripheral Pin Select Output Register 20 Register 3-90: RPOR21: Peripheral Pin Select Output Register 21 Register 3-91: RPOR22: Peripheral Pin Select Output Register 22 TABLE 3-40: Master PPS Input Control Registers TABLE 3-41: Master PPS Output Control Registers(1) 3.7 Deadman Timer (DMT) (Master Only) TABLE 3-42: DMT Module Overview FIGURE 3-22: Deadman Timer Block Diagram 3.7.1 Deadman Timer Control/Status Registers Register 3-92: DMTCON: Deadman Timer Control Register Register 3-93: DMTPRECLR: Deadman Timer Preclear Register Register 3-94: DMTCLR: Deadman Timer Clear Register Register 3-95: DMTSTAT: Deadman Timer Status Register Register 3-96: DMTCNTL: Deadman Timer Count Register Low Register 3-97: DMTCNTH: Deadman Timer Count Register High Register 3-98: DMTPSCNTL: DMT Post-Configure Count Status Register Low Register 3-99: DMTPSCNTH: DMT Post-Configure Count Status Register High Register 3-100: DMTPSINTVL: DMT Post-Configure Interval Status Register Low Register 3-101: DMTPSINTVH: DMT Post-Configure Interval Status Register High Register 3-102: DMTHOLDREG: DMT Hold Register(1) 3.8 Controller Area Network (CAN FD) Module (Master Only) TABLE 3-43: CAN FD Module Overview 3.8.1 Features FIGURE 3-23: CAN FD Module Block Diagram 3.8.2 CAN Control/Status Registers Register 3-103: C1CONH: CAN Control Register High(2) Register 3-104: C1CONL: CAN Control Register Low(2) Register 3-105: C1NBTCFGH: CAN Nominal Bit Time Configuration Register High(1,2) Register 3-106: C1NBTCFGL: CAN Nominal Bit Time Configuration Register Low(1,2) Register 3-107: C1DBTCFGH: CAN Data Bit Time Configuration Register High(1,2) Register 3-108: C1DBTCFGL: CAN Data Bit Time Configuration Register Low(1,2) Register 3-109: C1TDCH: CAN Transmitter Delay Compensation Register High(1,2) Register 3-110: C1TDCL: CAN Transmitter Delay Compensation Register Low(1,2) Register 3-111: C1TBCH: CAN Time Base Counter Register High(1,2,3) Register 3-112: C1TBCL: CAN Time Base Counter Register Low(1,2,3) Register 3-113: C1TSCONH: CAN Timestamp Control Register High(1) Register 3-114: C1TSCONL: CAN Timestamp Control Register Low(1) Register 3-115: C1VECH: CAN Interrupt Code Register High(1) Register 3-116: C1VECL: CAN Interrupt Code Register Low(1) Register 3-117: C1INTH: CAN Interrupt Register High(1) Register 3-118: C1INTL: CAN Interrupt Register Low(2) Register 3-119: C1RXIFH: CAN Receive Interrupt Status Register High(1,2) Register 3-120: C1RXIFL: CAN Receive Interrupt Status Register Low(1,2) Register 3-121: C1RXOVIFH: CAN Receive Overflow Interrupt Status Register High(1,2) Register 3-122: C1RXOVIFL: CAN Receive Overflow Interrupt Status Register Low(1,2) Register 3-123: C1TXIFH: CAN Transmit Interrupt Status Register High(1,2) Register 3-124: C1TXIFL: CAN Transmit Interrupt Status Register Low(1,3) Register 3-125: C1TXATIFH: CAN Transmit Attempt Interrupt Status Register High(1,2) Register 3-126: C1TXATIFL: CAN Transmit Attempt Interrupt Status Register Low(1,3) Register 3-127: C1TXREQH: CAN Transmit Request Register High(1) Register 3-128: C1TXREQL: CAN Transmit Request Register Low(1) Register 3-129: C1FIFOBAH: CAN Message Memory Base Address Register High(1) Register 3-130: C1FIFOBAL: CAN Message Memory Base Address Register Low(1) Register 3-131: C1TXQCONH: CAN Transmit Queue Control Register High(2) Register 3-132: C1TXQCONL: CAN Transmit Queue Control Register Low(1) Register 3-133: C1TXQSTA: CAN Transmit Queue Status Register(3) Register 3-134: C1FIFOCONxH: CAN FIFO Control Register x (x = 1 to 7) High(2) Register 3-135: C1FIFOCONxL: CAN FIFO Control Register x (x = 1 to 7) Low(2) Register 3-136: C1FIFOSTAx: CAN FIFO Status Register x (x = 1 to 7)(4) Register 3-137: C1TEFCONH: CAN Transmit Event FIFO Control Register High(2) Register 3-138: C1TEFCONL: CAN Transmit Event FIFO Control Register Low(2) Register 3-139: C1TEFSTA: CAN Transmit Event FIFO Status Register(2) Register 3-140: C1FIFOUAHx: CAN FIFO User Address High x (x = 1 to 7) Register(1,2) Register 3-141: C1FIFOUALx: CAN FIFO User Address Low x (x = 1 to 7) Register(1,2) Register 3-142: C1TEFUAH: CAN Transmit Event FIFO User Address Register High(1,2) Register 3-143: C1TEFUAL: CAN Transmit Event FIFO User Address Register Low(1,2) Register 3-144: C1TXQUAH: CAN Transmit Queue User Address Register High(1,2) Register 3-145: C1TXQUAL: CAN Transmit Queue User Address Register Low(1,2) Register 3-146: C1TRECH: CAN Transmit/Receive Error Count Register High(1) Register 3-147: C1TRECL: CAN Transmit/Receive Error Count Register Low(1) Register 3-148: C1BDIAG0H: CAN Bus Diagnostics Register 0 High(1) Register 3-149: C1BDIAG0L: CAN Bus Diagnostics Register 0 Low(1) Register 3-150: C1BDIAG1H: CAN Bus Diagnostics Register 1 High(1) Register 3-151: C1BDIAG1L: CAN Bus Diagnostics Register 1 Low(1) Register 3-152: C1FLTCONxH: CAN Filter Control Register x High (x = 0 to 3; c = 2, 6, 10, 14; d = 3, 7, 11, 15)(1) Register 3-153: C1FLTCONxL: CAN Filter Control Register x Low (x = 0 to 3; a = 0, 4, 8, 12; b = 1, 5, 9, 13)(1) Register 3-154: C1FLTOBJxH: CAN Filter Object Register x High (x = 0 to 15)(1) Register 3-155: C1FLTOBJxL: CAN Filter Object Register x Low (x = 0 to 15)(1) Register 3-156: C1MASKxH: CAN Mask Register x High (x = 0 to 15)(1) Register 3-157: C1MASKxL: CAN Mask Register x Low (x = 0 to 15)(1) 3.9 High-Speed, 12-Bit Analog-to-Digital Converter (Master ADC) 3.9.1 Master ADC Features Overview FIGURE 3-24: ADC Module Block Diagram FIGURE 3-25: Shared Core Block Diagram 3.9.2 Temperature Sensor 3.9.3 Analog-to-Digital Converter Resources 3.9.4 ADC Control/Status Registers Register 3-158: ADCON1L: ADC Control Register 1 Low Register 3-159: ADCON1H: ADC Control Register 1 High Register 3-160: ADCON2L: ADC Control Register 2 Low Register 3-161: ADCON2H: ADC Control Register 2 High Register 3-162: ADCON3L: ADC Control Register 3 Low Register 3-163: ADCON3H: ADC Control Register 3 High Register 3-164: ADCON5L: ADC Control Register 5 Low Register 3-165: ADCON5H: ADC Control Register 5 High Register 3-166: ADLVLTRGL: ADC Level-Sensitive Trigger Control Register Low Register 3-167: ADLVLTRGH: ADC Level-Sensitive Trigger Control Register High Register 3-168: ADEIEL: ADC Early Interrupt Enable Register Low Register 3-169: ADEIEH: ADC Early Interrupt Enable Register High Register 3-170: ADEISTATL: ADC Early Interrupt Status Register Low Register 3-171: ADEISTATH: ADC Early Interrupt Status Register High Register 3-172: ADMOD0L: ADC Input Mode Control Register 0 Low Register 3-173: ADMOD0H: ADC Input Mode Control Register 0 High Register 3-174: ADMOD1L: ADC Input Mode Control Register 1 Low Register 3-175: ADIEL: ADC Interrupt Enable Register Low Register 3-176: ADIEH: ADC Interrupt Enable Register High Register 3-177: ADSTATL: ADC Data Ready Status Register Low Register 3-178: ADSTATH: ADC Data Ready Status Register High Register 3-179: ADTRIGnL and ADTRIGnH: ADC Channel Trigger n(x) Selection Registers Low and High (x = 0 to 19; n = 0 to 4) Register 3-180: ADCMPxCON: ADC Digital Comparator x Control Register (x = 0, 1, 2, 3) Register 3-181: ADCMPxENL: ADC Digital Comparator x Channel Enable Register Low (x = 0, 1, 2, 3) Register 3-182: ADCMPxENH: ADC Digital Comparator x Channel Enable Register High (x = 0, 1, 2, 3) Register 3-183: ADFLxCON: ADC Digital Filter x Control Register (x = 0, 1, 2, 3) 3.10 Peripheral Trigger Generator (PTG) TABLE 3-44: PTG Module Overview 3.10.1 Features FIGURE 3-26: PTG Block Diagram 3.10.2 PTG Control/Status Registers Register 3-184: PTGCST: PTG Control/Status Low Register Register 3-185: PTGCON: PTG Control/Status High Register Register 3-186: PTGBTE: PTG Broadcast Trigger Enable Low Register(1) Register 3-187: PTGBTEH: PTG Broadcast Trigger Enable High Register(1) Register 3-188: PTGHOLD: PTG Hold Register(1) Register 3-189: PTGT0LIM: PTG Timer0 Limit Register(1) Register 3-190: PTGT1LIM: PTG Timer1 Limit Register(1) Register 3-191: PTGSDLIM: PTG Step Delay Limit Register(1) Register 3-192: PTGC0LIM: PTG Counter 0 Limit Register(1) Register 3-193: PTGC1LIM: PTG Counter 1 Limit Register(1) Register 3-194: PTGADJ: PTG Adjust Register(1) Register 3-195: PTGL0: PTG Literal 0 Register(1,2) Register 3-196: PTGQPTR: PTG Step Queue Pointer Register(1) Register 3-197: PTGQUEn: PTG Step Queue n Pointer Register (n = 0-15)(1,2) TABLE 3-45: PTG Step Command Format and Description TABLE 3-46: PTG Command Options TABLE 3-47: PTG Input Descriptions TABLE 3-48: PTG Output Descriptions 4.0 Slave Modules 4.1 Slave CPU 4.1.1 Registers 4.1.2 Instruction Set 4.1.3 Data Space Addressing 4.1.4 Addressing Modes FIGURE 4-1: dsPIC33CH128MP508S1 Family (Slave) CPU Block Diagram 4.1.5 Programmer’s Model TABLE 4-1: Programmer’s Model Register Descriptions FIGURE 4-2: Programmer’s Model (Slave) 4.1.6 CPU Resources 4.1.7 CPU Control/Status Registers Register 4-1: SR: CPU STATUS Register Register 4-2: CORCON: Core Control Register Register 4-3: CTXTSTAT: CPU W Register Context Status Register 4.1.8 Arithmetic Logic Unit (ALU) 4.1.9 DSP Engine TABLE 4-2: DSP Instructions Summary 4.2 Slave Memory Organization 4.2.1 Program Address Space FIGURE 4-3: PRAM (Program Memory) for Slave dsPIC33CH128MP508S1 Devices FIGURE 4-4: Program Memory Organization 4.2.2 Data Address Space (Slave) FIGURE 4-5: Data Memory Map for Slave dsPIC33CH128MP508S1 Devices 4.2.3 Memory Resources 4.2.4 SFR Maps TABLE 4-3: Slave SFR Block 000h TABLE 4-4: Slave SFR Block 100h TABLE 4-5: Slave SFR Block 200h TABLE 4-6: Slave SFR Block 300h TABLE 4-7: Slave SFR Block 400h TABLE 4-8: Slave SFR Block 800h TABLE 4-9: Slave SFR Block 900h TABLE 4-10: Slave SFR Block A00h TABLE 4-11: Slave SFR Block B00h TABLE 4-12: Slave SFR Block C00h TABLE 4-13: Slave SFR Block D00h TABLE 4-14: Slave SFR Block E00h TABLE 4-15: Slave SFR Block F00h FIGURE 4-6: Program Space Visibility (PSV) Read Address Generation FIGURE 4-7: Paged Data Memory Space TABLE 4-16: Overflow and Underflow Scenarios at Page 0 and PSV Space Boundaries(2,3,4) FIGURE 4-8: CALL Stack Frame 4.2.5 Instruction Addressing Modes TABLE 4-17: Fundamental Addressing Modes Supported 4.2.6 Modulo Addressing FIGURE 4-9: Modulo Addressing Operation Example 4.2.7 Bit-Reversed Addressing FIGURE 4-10: Bit-Reversed Addressing Example TABLE 4-18: Bit-Reversed Addressing Sequence (16-Entry) 4.2.8 Interfacing Program and Data Memory Spaces TABLE 4-19: Program Space Address Construction FIGURE 4-11: Data Access from Program Space Address Generation FIGURE 4-12: Accessing Program Memory with Table Instructions 4.3 Slave PRAM Program Memory 4.3.1 PRAM Programming Operations 4.3.2 Master to Slave Image Loading (MSIL) 4.3.3 Using Development Tool Supported Functions EXAMPLE 4-1: Slave PRAM Load and Verify Routine EXAMPLE 4-2: Slave Start and Stop Example 4.3.4 PRAM Dual Partition Considerations 4.3.5 Error Correcting Code (ECC) 4.3.6 Control Registers 4.3.7 Slave Program Memory Control/Status Registers Register 4-4: NVMCON: Program Memory Slave Control Register Register 4-5: NVMADR: Slave Program Memory Lower Address Register Register 4-6: NVMADRU: Slave Program Memory Upper Address Register Register 4-7: NVMKEY: Slave Nonvolatile Memory Key Register Register 4-8: NVMSRCADRL: Slave NVM Source Data Address Register Low Register 4-9: NVMSRCADRH: Slave NVM Source Data Address Register High 4.3.8 Slave ECC Control/Status Registers Register 4-10: ECCCONL: ECC Fault Injection Configuration Register Low Register 4-11: ECCCONH: ECC Fault Injection Configuration Register High Register 4-12: ECCADDRL: ECC Fault Inject Address Compare Register Low Register 4-13: ECCADDRH: ECC Fault Inject Address Compare Register High Register 4-14: ECCSTATL: ECC System Status Display Register Low Register 4-15: ECCSTATH: ECC System Status Display Register High 4.4 Slave Resets FIGURE 4-13: Reset System Block Diagram 4.4.1 Reset Resources 4.4.2 Slave Reset Control Register Register 4-16: RCON: Reset Control Register(1) 4.5 Slave Interrupt Controller 4.5.1 Interrupt Vector Table 4.5.2 Reset Sequence FIGURE 4-14: dsPIC33CH128MP508S1 Family Interrupt Vector Table TABLE 4-20: Trap Table TABLE 4-21: Slave Interrupt Vector Details(1) TABLE 4-22: Slave Interrupt Flag Registers TABLE 4-23: Slave Interrupt Enable Registers TABLE 4-24: Slave Interrupt Priority Registers 4.5.3 Interrupt Resources 4.5.4 Interrupt Control and Status Registers 4.5.5 INTTREG 4.5.6 Status/Control Registers 4.5.7 Cross Core Interrupts 4.5.8 Slave Interrupt Control/Status Registers Register 4-17: SR: CPU STATUS Register(1) Register 4-18: CORCON: Slave Core Control Register(1) Register 4-19: INTCON1: Slave Interrupt Control Register 1 Register 4-20: INTCON2: Slave Interrupt Control Register 2 Register 4-21: INTCON3: Slave Interrupt Control Register 3 Register 4-22: INTCON4: Slave Interrupt Control Register 4 Register 4-23: INTTREG: Slave Interrupt Control and Status Register 4.6 Slave I/O Ports 4.6.1 Parallel I/O (PIO) Ports TABLE 4-25: Pin and ANSELx Availability FIGURE 4-15: Block Diagram of a Typical Shared Port Structure 4.6.2 Configuring Analog and Digital Port Pins 4.6.3 Slave Port Control/Status Registers Register 4-24: ANSELx: Analog Select for PORTx Register Register 4-25: TRISx: Output Enable for PORTx Register Register 4-26: PORTx: Input Data for PORTx Register Register 4-27: LATx: Output Data for PORTx Register Register 4-28: ODCx: Open-Drain Enable for PORTx Register Register 4-29: CNPUx: Change Notification Pull-up Enable for PORTx Register Register 4-30: CNPDx: Change Notification Pull-Down Enable for PORTx Register Register 4-31: CNCONx: Change Notification Control for PORTx Register Register 4-32: CNEN0x: Interrupt Change Notification Enable for PORTx Register Register 4-33: CNSTATx: Interrupt Change Notification Status for PORTx Register Register 4-34: CNEN1x: Interrupt Change Notification Edge Select for PORTx Register Register 4-35: CNFx: Interrupt Change Notification Flag for PORTx Register 4.6.4 Input Change Notification (ICN) TABLE 4-26: Change Notification Event Options EXAMPLE 4-3: Port Write/Read Example 4.6.5 Peripheral Pin Select (PPS) FIGURE 4-16: Remappable Input for U1RX EXAMPLE 4-4: Configuring UART1 Input and Output Functions TABLE 4-27: Slave Remappable Pin Inputs TABLE 4-28: Selectable Input Sources (Maps Input to Function) TABLE 4-29: Slave PPS Input Control Registers FIGURE 4-17: Multiplexing Remappable Outputs for S1RPn TABLE 4-30: Slave Remappable Output Pin Registers TABLE 4-31: Output Selection for Remappable Pins (S1RPn) TABLE 4-32: Slave PPS Output Control Registers 4.6.6 I/O Helpful Tips 4.6.7 I/O Ports Resources 4.6.8 Peripheral Pin Select Registers Register 4-36: RPCON: Peripheral Remapping Configuration Register Register 4-37: RPINR0: Peripheral Pin Select Input Register 0 Register 4-38: RPINR1: Peripheral Pin Select Input Register 1 Register 4-39: RPINR2: Peripheral Pin Select Input Register 2 Register 4-40: RPINR3: Peripheral Pin Select Input Register 3 Register 4-41: RPINR4: Peripheral Pin Select Input Register 4 Register 4-42: RPINR5: Peripheral Pin Select Input Register 5 Register 4-43: RPINR6: Peripheral Pin Select Input Register 6 Register 4-44: RPINR11: Peripheral Pin Select Input Register 11 Register 4-45: RPINR12: Peripheral Pin Select Input Register 12 Register 4-46: RPINR13: Peripheral Pin Select Input Register 13 Register 4-47: RPINR14: Peripheral Pin Select Input Register 14 Register 4-48: RPINR15: Peripheral Pin Select Input Register 15 Register 4-49: RPINR18: Peripheral Pin Select Input Register 18 Register 4-50: RPINR20: Peripheral Pin Select Input Register 20 Register 4-51: RPINR21: Peripheral Pin Select Input Register 21 Register 4-52: RPINR23: Peripheral Pin Select Input Register 23 Register 4-53: RPINR37: Peripheral Pin Select Input Register 37 Register 4-54: RPINR38: Peripheral Pin Select Input Register 38 Register 4-55: RPINR42: Peripheral Pin Select Input Register 42 Register 4-56: RPINR43: Peripheral Pin Select Input Register 43 Register 4-57: RPINR44: Peripheral Pin Select Input Register 44 Register 4-58: RPINR45: Peripheral Pin Select Input Register 45 Register 4-59: RPINR46: Peripheral Pin Select Input Register 46 Register 4-60: RPINR47: Peripheral Pin Select Input Register 47 Register 4-61: RPOR0: Peripheral Pin Select Output Register 0 Register 4-62: RPOR1: Peripheral Pin Select Output Register 1 Register 4-63: RPOR2: Peripheral Pin Select Output Register 2 Register 4-64: RPOR3: Peripheral Pin Select Output Register 3 Register 4-65: RPOR4: Peripheral Pin Select Output Register 4 Register 4-66: RPOR5: Peripheral Pin Select Output Register 5 Register 4-67: RPOR6: Peripheral Pin Select Output Register 6 Register 4-68: RPOR7: Peripheral Pin Select Output Register 7 Register 4-69: RPOR8: Peripheral Pin Select Output Register 8 Register 4-70: RPOR9: Peripheral Pin Select Output Register 9 Register 4-71: RPOR10: Peripheral Pin Select Output Register 10 Register 4-72: RPOR11: Peripheral Pin Select Output Register 11 Register 4-73: RPOR12: Peripheral Pin Select Output Register 12 Register 4-74: RPOR13: Peripheral Pin Select Output Register 13 Register 4-75: RPOR14: Peripheral Pin Select Output Register 14 Register 4-76: RPOR15: Peripheral Pin Select Output Register 15 Register 4-77: RPOR16: Peripheral Pin Select Output Register 16 Register 4-78: RPOR17: Peripheral Pin Select Output Register 17 Register 4-79: RPOR18: Peripheral Pin Select Output Register 18 Register 4-80: RPOR19: Peripheral Pin Select Output Register 19 Register 4-81: RPOR20: Peripheral Pin Select Output Register 20 Register 4-82: RPOR21: Peripheral Pin Select Output Register 21 Register 4-83: RPOR22: Peripheral Pin Select Output Register 22 TABLE 4-33: PORTA Register Summary TABLE 4-34: PORTB Register Summary TABLE 4-35: PORTC Register Summary TABLE 4-36: PORTD Register Summary TABLE 4-37: PORTE Register Summary 4.7 High-Speed, 12-Bit Analog-to-Digital Converter (Slave ADC) 4.7.1 Slave ADC Features Overview FIGURE 4-18: ADC Module Block Diagram FIGURE 4-19: ADC Shared Core Block Diagram FIGURE 4-20: Dedicated ADC Core 4.7.2 Temperature Sensor 4.7.3 Analog-to-Digital Converter Resources 4.7.4 ADC Control/Status Registers Register 4-84: ADCON1L: ADC Control Register 1 Low Register 4-85: ADCON1H: ADC Control Register 1 High Register 4-86: ADCON2L: ADC Control Register 2 Low Register 4-87: ADCON2H: ADC Control Register 2 High Register 4-88: ADCON3L: ADC Control Register 3 Low Register 4-89: ADCON3H: ADC Control Register 3 High Register 4-90: ADCON4L: ADC Control Register 4 Low Register 4-91: ADCON4H: ADC Control Register 4 High Register 4-92: ADCON5L: ADC Control Register 5 Low Register 4-93: ADCON5H: ADC Control Register 5 High Register 4-94: ADCORExL: Dedicated ADC Core x Control Register Low (x = 0 to 1) Register 4-95: ADCORExH: Dedicated ADC Core x Control Register High (x = 0 to 1) Register 4-96: ADLVLTRGL: ADC Level-Sensitive Trigger Control Register Low Register 4-97: ADLVLTRGH: ADC Level-Sensitive Trigger Control Register High Register 4-98: ADEIEL: ADC Early Interrupt Enable Register Low Register 4-99: ADEIEH: ADC Early Interrupt Enable Register High Register 4-100: ADEISTATL: ADC Early Interrupt Status Register Low Register 4-101: ADEISTATH: ADC Early Interrupt Status Register High Register 4-102: ADMOD0L: ADC Input Mode Control Register 0 Low Register 4-103: ADMOD0H: ADC Input Mode Control Register 0 High Register 4-104: ADMOD1L: ADC Input Mode Control Register 1 Low Register 4-105: ADIEL: ADC Interrupt Enable Register Low Register 4-106: ADIEH: ADC Interrupt Enable Register High Register 4-107: ADSTATL: ADC Data Ready Status Register Low Register 4-108: ADSTATH: ADC Data Ready Status Register High Register 4-109: ADTRIGnL/ADTRIGnH: ADC Channel Trigger n(x) Selection Registers Low and High (x = 0 TO 19; n = 0 TO 4) Register 4-110: ADCAL1H: ADC Calibration Register 1 High Register 4-111: ADCMPxCON: ADC Digital Comparator x Control Register (x = 0, 1, 2, 3) Register 4-112: ADCMPxENL: ADC Digital Comparator x Channel Enable Register Low (x = 0, 1, 2, 3) Register 4-113: ADCMPxENH: ADC Digital Comparator x Channel Enable Register High (x = 0, 1, 2, 3) Register 4-114: ADFLxCON: ADC Digital Filter x Control Register (x = 0, 1, 2, 3) 4.8 Programmable Gain Amplifier (PGA) Slave TABLE 4-38: PGA Module Overview(1) FIGURE 4-21: PGAx Module Block Diagram 4.8.1 Module Description FIGURE 4-22: PGAx Functional Block Diagram 4.8.2 PGA Resources 4.8.3 PGA Control Registers Register 4-115: PGAxCON: PGAx Control Register Register 4-116: PGAxCAL: PGAx Calibration Register 5.0 Master Slave Interface (MSI) 5.1 Master MSI Control Registers Register 5-1: MSI1CON: MSI1 Master Control Register Register 5-2: MSI1STAT: MSI1 Master Status Register Register 5-3: MSI1KEY: MSI1 Master Interlock Key Register Register 5-4: MSI1MBXS: MSI1 Master Mailbox Data Transfer Status Register Register 5-5: MSI1MBXnD: MSI1 Master Mailbox n Data Register (n = 0 to 15) Register 5-6: MSI1FIFOCS: MSI1 Master FIFO Control/Status Register Register 5-7: MRSWFDATA: Master Read (Slave Write) FIFO Data Register Register 5-8: MWSRFDATA: Master Write (Slave Read) FIFO Data Register 5.2 Slave MSI Control Registers Register 5-9: SI1CON: MSI1 Slave Control Register Register 5-10: SI1STAT: MSI1 Slave Status Register Register 5-11: SI1MBX: MSI1 Slave Mailbox Data Transfer Status Register Register 5-12: SI1MBXnD: MSI1 Slave Mailbox n Data Register (n = 0 to 15) Register 5-13: SI1FIFOCS: MSI1 Slave FIFO Status Register Register 5-14: SWMRFDATA: Slave Write (Master Read) FIFO Data Register Register 5-15: SRMWFDATA: Slave Read (Master Write) FIFO Data Register 5.3 Slave Processor Control 5.3.1 Slave Enable (SLVEN) Control EXAMPLE 5-1: MSI Enable Operation EXAMPLE 5-2: MSI Enable Operation in C Code 5.4 Slave Reset Coupling Control TABLE 5-1: Application Mode SLVEN Reset Control Truth Table 5.4.1 Inter-Processor Interrupt Request and Acknowledge 5.4.2 Read Address Pointers for FIFOs 6.0 Oscillator with High-Frequency PLL FIGURE 6-1: Master and Slave Core Shared Clock Sources Block Diagram FIGURE 6-2: Master Core Oscillator Subsystem FIGURE 6-3: Slave Core Oscillator Subsystem 6.1 Primary PLL FIGURE 6-4: Master/Slave Core PLL and VCO Detail EQUATION 6-1: Master/Slave Core Fvco Calculation EQUATION 6-2: Master/Slave Core Fpllo Calculation EXAMPLE 6-1: Code Example for Using Master Primary PLL with 8 MHz Internal FRC EXAMPLE 6-2: Code Example for Using Slave Primary PLL with 8 MHz Internal FRC 6.2 Auxiliary PLL FIGURE 6-5: Master/Slave Core APLL and VCO Detail EQUATION 6-3: Master/Slave Core AFvco Calculation EQUATION 6-4: Master/Slave Core AFpllo Calculation EXAMPLE 6-3: Code Example for Using Master or Slave Auxiliary PLL with the Internal FRC Oscillator 6.3 CPU Clocking FIGURE 6-6: Clock and Instruction Cycle Timing 6.4 Primary Oscillator (POSC) 6.5 Internal Fast RC (FRC) Oscillator 6.6 Low-Power RC (LPRC) Oscillator 6.7 Backup Internal Fast RC (BFRC) Oscillator 6.8 Reference Clock Output FIGURE 6-7: Reference Clock Generator EQUATION 6-5: Calculating Frequency Output 6.9 OSCCON Unlock Sequence EXAMPLE 6-4: Code Example for Using Master PLL (50 MIPS) with Primary Oscillator (POSC) EXAMPLE 6-5: Code Example for Using Slave PLL (60 MIPS) with Primary Oscillator (POSC) EXAMPLE 6-6: Code Example for Using Master PLL (50 MIPS) with 8 MHz Internal FRC EXAMPLE 6-7: Code Example for Using Slave PLL (60 MIPS) with 8 MHz Internal FRC 6.10 Master Oscillator Configuration Registers TABLE 6-1: Configuration Bit Values for Clock Selection for the Master 6.11 Slave Oscillator Configuration Registers TABLE 6-2: Configuration Bit Values for Clock Selection for the Slave TABLE 6-3: OSCO Function for the Master and Slave Core(1) 6.12 Master Special Function Registers 6.12.1 Master Oscillator Control Registers Register 6-1: OSCCON: Oscillator Control Register (Master)(1) Register 6-2: CLKDIV: Clock Divider Register (Master) Register 6-3: PLLFBD: PLL Feedback Divider Register (Master) Register 6-4: OSCTUN: FRC Oscillator Tuning Register (Master) Register 6-5: PLLDIV: PLL Output Divider Register (Master) Register 6-6: ACLKCON1: Auxiliary Clock Control Register (Master) Register 6-7: APLLFBD1: APLL Feedback Divider Register (Master) Register 6-8: APLLDIV1: APLL Output Divider Register (Master) Register 6-9: CANCLKCON: CAN Clock Control Register Register 6-10: REFOCONL: Reference Clock Control Low Register (Master) Register 6-11: REFOCONH: Reference Clock Control High Register (Master) Register 6-12: REFOTRIM: Reference Oscillator Trim Register (Master) 6.13 Slave Special Function Registers 6.13.1 Slave Oscillator Control Registers Register 6-13: OSCCON: Oscillator Control Register (Slave)(1) Register 6-14: CLKDIV: Clock Divider Register (Slave) Register 6-15: PLLFBD: PLL Feedback Divider Register (Slave) Register 6-16: PLLDIV: PLL Output Divider Register (Slave) Register 6-17: ACLKCON1: Auxiliary Clock Control Register (Slave) Register 6-18: APLLFBD1: APLL Feedback Divider Register (Slave) Register 6-19: APLLDIV: APLL Output Divider Register (Slave) Register 6-20: REFOCONL: Reference Clock Control Low Register (Slave) Register 6-21: REFOCONH: Reference Clock Control High Register (Slave) 7.0 Power-Saving Features (Master and Slave) 7.1 Clock Frequency and Clock Switching 7.2 Instruction-Based Power-Saving Modes EXAMPLE 7-1: PWRSAV Instruction Syntax 7.2.1 Sleep Mode 7.2.2 Idle Mode 7.2.3 Interrupts Coincident with Power Save Instructions 7.3 Doze Mode 7.4 Peripheral Module Disable 7.5 Power-Saving Resources 7.5.1 Key Resources 7.6 PMD Control Registers Register 7-1: PMD1: Master Peripheral Module Disable 1 Control Register Low Register 7-2: PMD2: Master Peripheral Module Disable 2 Control Register High Register 7-3: PMD3: Master Peripheral Module Disable 3 Control Register Low(1) Register 7-4: PMD4: Master Peripheral Module Disable 4 Control Register Register 7-5: PMD6: Master Peripheral Module Disable 6 Control Register High Register 7-6: PMD7: Master Peripheral Module Disable 7 Control Register Low Register 7-7: PMD8: Master Peripheral Module Disable 8 Control Register(1) Register 7-8: PMDCON: Slave PMD Control Register Register 7-9: PMD1: Slave Peripheral Module Disable 1 Control Register Register 7-10: PMD2: Slave Peripheral Module Disable 2 Control Register Register 7-11: PMD4: Slave Peripheral Module Disable 4 Control Register Register 7-12: PMD6: Slave Peripheral Module Disable 6 Control Register High Register 7-13: PMD7: Slave Peripheral Module Disable 7 Control Register Low Register 7-14: PMD8: Slave Peripheral Module Disable 8 Control Register TABLE 7-1: Master PMD Registers TABLE 7-2: Slave PMD Registers 8.0 Direct Memory Access (DMA) Controller TABLE 8-1: DMA Module Overview FIGURE 8-1: DMA Functional Block Diagram 8.1 Summary of DMA Operations 8.1.1 Source and Destination 8.1.2 Data Size 8.1.3 Trigger Source 8.1.4 Transfer Mode 8.1.5 Addressing Modes FIGURE 8-2: Types of DMA Data Transfers 8.1.6 Channel Priority 8.2 Typical Setup 8.3 Peripheral Module Disable 8.4 Registers 8.5 DMA Control Registers Register 8-1: DMACON: DMA Engine Control Register Register 8-2: DMACHn: DMA Channel n Control Register Register 8-3: DMAINTn: DMA Channel n Interrupt Register TABLE 8-2: DMA Channel Trigger Sources (Master) TABLE 8-3: DMA Channel Trigger Sources (Slave) 9.0 High-Resolution PWM (HSPWM) with Fine Edge Placement TABLE 9-1: PWM Module Overview 9.1 Features 9.2 Architecture Overview FIGURE 9-1: PWM High-Level Block Diagram 9.3 PWM4H/L Output on Peripheral Pin Select 9.4 PWM Control Registers Register 9-1: PCLKCON: PWM Clock Control Register Register 9-2: FSCL: Frequency Scale Register Register 9-3: FSMINPER: Frequency Scaling Minimum Period Register Register 9-4: MPHASE: Master Phase Register Register 9-5: MDC: Master Duty Cycle Register Register 9-6: MPER: Master Period Register Register 9-7: CMBTRIGL: Combinational Trigger Register Low Register 9-8: CMBTRIGH: Combinational Trigger Register High Register 9-9: LOGCONy: Combinatorial PWM Logic Control Register y(2) Register 9-10: PWMEVTy: PWM Event Output Control Register y(5) Register 9-11: LFSR: Linear Feedback Shift Register Register 9-12: PGxCONL: PWM Generator x Control Register Low Register 9-13: PGxCONH: PWM Generator x Control Register High Register 9-14: PGxSTAT: PWM Generator x Status Register Register 9-15: PGxIOCONL: PWM Generator x I/O Control Register Low Register 9-16: PGxIOCONH: PWM Generator x I/O Control Register High Register 9-17: PGxyPCIL: PWM Generator xy PCI Register Low (x = PWM Generator #; y = F, CL, FF or S) Register 9-18: PGxyPCIH: PWM Generator xy PCI Register High (x = PWM Generator #; y = F, CL, FF or S) Register 9-19: PGxEVTL: PWM Generator x Event Register Low Register 9-20: PGxEVTH: PWM Generator x Event Register High Register 9-21: PGxLEBL: PWM Generator x Leading-Edge Blanking Register Low Register 9-22: PGxLEBH: PWM Generator x Leading-Edge Blanking Register High Register 9-23: PGxPHASE: PWM Generator x Phase Register Register 9-24: PGxDC: PWM Generator x Duty Cycle Register Register 9-25: PGxDCA: PWM Generator x Duty Cycle Adjustment Register Register 9-26: PGxPER: PWM Generator x Period Register Register 9-27: PGxTRIGA: PWM Generator x Trigger A Register Register 9-28: PGxTRIGB: PWM Generator x Trigger B Register Register 9-29: PGxTRIGC: PWM Generator x Trigger C Register Register 9-30: PGxDTL: PWM Generator x Dead-Time Register Low Register 9-31: PGxDTH: PWM Generator x Dead-Time Register High Register 9-32: PGxCAP: PWM Generator x Capture Register 10.0 Capture/Compare/PWM/ Timer Modules (SCCP) TABLE 10-1: SCCP Module Overview FIGURE 10-1: SCCPx Conceptual Block Diagram 10.1 Time Base Generator FIGURE 10-2: Timer Clock Generator 10.2 General Purpose Timer TABLE 10-2: Timer Operation Mode 10.2.1 Sync and Trigger Operation FIGURE 10-3: Dual 16-Bit Timer Mode FIGURE 10-4: 32-Bit Timer Mode 10.3 Output Compare Mode TABLE 10-3: Output Compare x/PWMx Modes FIGURE 10-5: Output Compare x Block Diagram 10.4 Input Capture Mode TABLE 10-4: Input Capture x Modes FIGURE 10-6: Input Capture x Block Diagram 10.5 Auxiliary Output TABLE 10-5: Auxiliary Output 10.6 SCCP Control/Status Registers Register 10-1: CCPxCON1L: CCPx Control 1 Low Registers Register 10-2: CCPxCON1H: CCPx Control 1 High Registers TABLE 10-6: Synchronization Sources (Master) TABLE 10-7: Synchronization Sources (Slave) Register 10-3: CCPxCON2L: CCPx Control 2 Low Registers TABLE 10-8: Auto-Shutdown and Gating Sources (Master) TABLE 10-9: Auto-Shutdown and Gating Sources (Slave) Register 10-4: CCPxCON2H: CCPx Control 2 High Registers Register 10-5: CCPxCON3H: CCPx Control 3 High Registers Register 10-6: CCPxSTATL: CCPx Status Register 11.0 High-Speed Analog Comparator with Slope Compensation DAC TABLE 11-1: Comparator/DAC Module Overview 11.1 Overview FIGURE 11-1: High-Speed Analog Comparator Module Block Diagram 11.2 Features Overview 11.3 DAC Control Registers Register 11-1: DACCTRL1L: DAC Control 1 Low Register Register 11-2: DACCTRL2H: DAC Control 2 High Register Register 11-3: DACCTRL2L: DAC Control 2 Low Register Register 11-4: DACxCONH: DACx Control High Register Register 11-5: DACxCONL: DACx Control Low Register Register 11-6: DACxDATH: DACx Data High Register Register 11-7: DACxDATL: DACx Data Low Register Register 11-8: SLPxCONH: DACx Slope Control High Register Register 11-9: SLPxCONL: DACx Slope Control Low Register Register 11-10: SLPxDAT: DACx Slope Data Register(1) 12.0 Quadrature Encoder Interface (QEI) (Master/Slave) TABLE 12-1: QEI Module Overview FIGURE 12-1: Quadrature Encoder Interface Signals TABLE 12-2: Truth Table for Quadrature Encoder FIGURE 12-2: Quadrature Encoder Interface (QEI) Module Block Diagram 12.1 QEI Control and Status Registers Register 12-1: QEIxCON: QEIx Control Register Register 12-2: QEIxIOCL: QEIx I/O Control Low Register Register 12-3: QEIxIOCH: QEIx I/O Control High Register Register 12-4: QEIxSTAT: QEIx Status Register Register 12-5: POSxCNTL: Position x Counter Register Low Register 12-6: POSxCNTH: Position x Counter Register High Register 12-7: POSxHLDL: Position x Counter Hold Register Low Register 12-8: POSxHLDH: Position x Counter Hold Register High Register 12-9: VELxCNTL: Velocity x Counter Register Low Register 12-10: VELxCNTH: Velocity x Counter Register High Register 12-11: VELxHLDL: Velocity x Counter Hold Register Low Register 12-12: VELxHLDH: Velocity x Counter Hold Register High Register 12-13: INTxTMRL: Interval x Timer Register Low Register 12-14: INTxTMRH: Interval x Timer Register High Register 12-15: INTXxHLDL: Index x Counter Hold Register Low Register 12-16: INTXxHLDH: Index x Counter Hold Register High Register 12-17: INDXxCNTL: Index x Counter Register Low Register 12-18: INDXxCNTH: Index x Counter Register High Register 12-19: INDXxHLDL: Index x Counter Hold Register Low Register 12-20: INDXxHLDH: Index x Counter Hold Register High Register 12-21: QEIxGECL: QEIx Greater Than or Equal Compare Register Low Register 12-22: QEIxGECH: QEIx Greater Than or Equal Compare Register High Register 12-23: QEIxLECL: QEIx Less than or Equal Compare Register Low Register 12-24: QEIxLECH: QEIx Less than or Equal Compare Register High 13.0 Universal Asynchronous Receiver Transmitter (UART) TABLE 13-1: UART Module Overview 13.1 Architectural Overview FIGURE 13-1: Simplified UARTx Block Diagram 13.2 Character Frame FIGURE 13-2: UART Character Frame 13.3 Data Buffers 13.4 Protocol Extensions 13.5 UART Control/Status Registers Register 13-1: UxMODE: UARTx Configuration Register Register 13-2: UxMODEH: UARTx Configuration Register High Register 13-3: UxSTA: UARTx Status Register Register 13-4: UxSTAH: UARTx Status Register High Register 13-5: UxBRG: UARTx Baud Rate Register Register 13-6: UxBRGH: UARTx Baud Rate Register High Register 13-7: UxRXREG: UARTx Receive Buffer Register Register 13-8: UxTXREG: UARTx Transmit Buffer Register Register 13-9: UxP1: UARTx Timing Parameter 1 Register Register 13-10: UxP2: UARTx Timing Parameter 2 Register Register 13-11: UxP3: UARTx Timing Parameter 3 Register Register 13-12: UxP3H: UARTx Timing Parameter 3 Register High Register 13-13: UxTXCHK: UARTx Transmit Checksum Register Register 13-14: UxRXCHK: UARTx Receive Checksum Register Register 13-15: UxSCCON: UARTx Smart Card Configuration Register Register 13-16: UxSCINT: UARTx Smart Card Interrupt Register Register 13-17: UxINT: UARTx Interrupt Register 14.0 Serial Peripheral Interface (SPI) TABLE 14-1: SPI Module Overview FIGURE 14-1: SPIx Module Block Diagram (Standard Mode) FIGURE 14-2: SPIx Module Block Diagram (Enhanced Mode) 14.1 SPI Control/Status Registers Register 14-1: SPIxCON1L: SPIx Control Register 1 Low Register 14-2: SPIxCON1H: SPIx Control Register 1 High Register 14-3: SPIxCON2L: SPIx Control Register 2 Low Register 14-4: SPIxSTATL: SPIx Status Register Low Register 14-5: SPIxSTATH: SPIx Status Register High Register 14-6: SPIxIMSKL: SPIx Interrupt Mask Register Low Register 14-7: SPIxIMSKH: SPIx Interrupt Mask Register High FIGURE 14-3: SPIx Master/Slave Connection (Standard Mode) FIGURE 14-4: SPIx Master/Slave Connection (Enhanced Buffer Modes) FIGURE 14-5: SPIx Master, Frame Master Connection Diagram FIGURE 14-6: SPIx Master, Frame Slave Connection Diagram FIGURE 14-7: SPIx Slave, Frame Master Connection Diagram FIGURE 14-8: SPIx Slave, Frame Slave Connection Diagram EQUATION 14-1: Relationship Between Device and SPIx Clock Speed 15.0 Inter-Integrated Circuit (I2C) 15.1 Communicating as a Master in a Single Master Environment FIGURE 15-1: I2Cx Block Diagram 15.2 Setting Baud Rate When Operating as a Bus Master EQUATION 15-1: Computing Baud Rate Reload Value(1,2,3) 15.3 Slave Address Masking TABLE 15-1: I2Cx Clock Rates(1,2) TABLE 15-2: I2Cx Reserved Addresses(1) 15.4 SMBus Support TABLE 15-3: I2C Pin Voltage Threshold 15.5 I2C Control/Status Registers Register 15-1: I2CxCONL: I2Cx Control Register Low Register 15-2: I2CxCONH: I2Cx Control Register High Register 15-3: I2CxSTAT: I2Cx Status Register Register 15-4: I2CxMSK: I2Cx Slave Mode Address Mask Register 16.0 Single-Edge Nibble Transmission (SENT) TABLE 16-1: SENT Module Overview 16.1 Module Introduction FIGURE 16-1: SENTx Module Block Diagram FIGURE 16-2: SENTx Protocol Data Frames 16.2 Transmit Mode EQUATION 16-1: Tick Period Calculation EQUATION 16-2: Frame Time Calculations 16.2.1 Transmit Mode Configuration 16.3 Receive Mode EQUATION 16-3: SYNCMIN[15:0] and SYNCMAX[15:0] Calculations 16.3.1 Receive Mode Configuration 16.4 SENT Control/Status Registers Register 16-1: SENTxCON1: SENTx Control Register 1 Register 16-2: SENTxSTAT: SENTx Status Register Register 16-3: SENTxDATL: SENTx Receive Data Register Low(1) Register 16-4: SENTxDATH: SENTx Receive Data Register High(1) 17.0 Timer1 TABLE 17-1: Timer1 Module Overview FIGURE 17-1: 16-Bit Timer1 Module Block Diagram 17.1 Timer1 Control Register Register 17-1: T1CON: Timer1 Control Register 18.0 Configurable Logic Cell (CLC) TABLE 18-1: CLC Module Overview FIGURE 18-1: CLCx Module FIGURE 18-2: CLCx Logic Function Combinatorial Options FIGURE 18-3: CLCx Input Source Selection Diagram(1,2) 18.1 Control Registers Register 18-1: CLCxCONL: CLCx Control Register (Low) Register 18-2: CLCxCONH: CLCx Control Register (High) Register 18-3: CLCxSEL: CLCx Input MUX Select Register Register 18-4: CLCxGLSL: CLCx Gate Logic Input Select Low Register Register 18-5: CLCxGLSH: CLCx Gate Logic Input Select High Register 19.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator TABLE 19-1: CRC Module Overview FIGURE 19-1: CRC Module Block Diagram 19.1 CRC Control Registers Register 19-1: CRCCONL: CRC Control Register Low Register 19-2: CRCCONH: CRC Control Register High Register 19-3: CRCXORL: CRC XOR Polynomial Register, Low Byte Register 19-4: CRCXORH: CRC XOR Polynomial Register, High Byte 20.0 Current Bias Generator (CBG) TABLE 20-1: CBG Channel Availability FIGURE 20-1: Constant-Current Source Module Block Diagram(2) 20.1 Current Bias Generator Control Registers Register 20-1: BIASCON: Current Bias Generator Control Register Register 20-2: IBIASCONH: Current Bias Generator 50 μA Current Source Control High Register Register 20-3: IBIASCONL: Current Bias Generator 50 μA Current Source Control Low Register 21.0 Special Features 21.1 Configuration Bits TABLE 21-1: Configuration Word Addresses TABLE 21-2: Master Configuration Registers Map TABLE 21-3: Slave Configuration Registers Map Register 21-1: FSEC Configuration Register Register 21-2: FBSLIM Configuration Register Register 21-3: FSIGN Configuration Register Register 21-4: FOSCSEL Configuration Register Register 21-5: FOSC Configuration Register Register 21-6: FWDT Configuration Register Register 21-7: FPOR Configuration Register Register 21-8: FICD Configuration Register Register 21-9: FDMTIVTL Configuration Register Register 21-10: FDMTIVTH Configuration Register Register 21-11: FDMTCNTL Configuration Register Register 21-12: FDMTCNTH Configuration Register Register 21-13: FDMT Configuration Register Register 21-14: FDEVOPT Configuration Register Register 21-15: FALTREG Configuration Register Register 21-16: FMBXM Configuration Register Register 21-17: FMBXHS1 Configuration Register Register 21-18: FMBXHS2 Configuration Register Register 21-19: FMBXHSEN Configuration Register Register 21-20: FCFGPRA0: PORTA Configuration Register Register 21-21: FCFGPRB0: PORTB Configuration Register Register 21-22: FCFGPRC0: PORTC Configuration Register Register 21-23: FCFGPRD0: PORTD Configuration Register Register 21-24: FCFGPRE0: PORTE Configuration Register Register 21-25: FS1OSCSEL Configuration Register (Slave) Register 21-26: FS1OSC Configuration Register (Slave) Register 21-27: FS1WDT Configuration Register (Slave) Register 21-28: FS1POR Configuration Register (Slave) Register 21-29: FS1ICD Configuration Register (Slave) Register 21-30: FS1DEVOPT Configuration Register (Slave) Register 21-31: FS1ALTREG Configuration Register (Slave) 21.2 Device Calibration and Identification TABLE 21-4: Device Calibration Addresses(1) Register 21-32: DEVREV: Device Revision Register Register 21-33: DEVID: Device ID Registers TABLE 21-5: Device Variants 21.3 User OTP Memory 21.4 On-Chip Voltage Regulators FIGURE 21-1: Internal Regulator 21.5 Regulator Control and Sleep Mode Register 21-34: VREGCON: Voltage Regulator Control Register 21.6 Limiting Dynamic Load Changes 21.7 Brown-out Reset (BOR) 21.8 Dual Watchdog Timer (WDT) TABLE 21-6: Dual WDT Module Overview FIGURE 21-2: Watchdog Timer Block Diagram 21.9 Watchdog Timer Control Registers Register 21-35: WDTCONL: Watchdog Timer Control Register Low Register 21-36: WDTCONH: Watchdog Timer Control Register High Register 21-37: RCON: Reset Control Register(1) 21.10 JTAG Interface 21.11 In-Circuit Serial Programming™ (ICSP™) 21.12 In-Circuit Debugger 21.12.1 Master Only Debug 21.12.2 Slave Only Debug 21.12.3 Dual Debug (Both Master and Slave are Debugged) 21.13 Code Protection and CodeGuard™ Security – Master Flash FIGURE 21-3: Security Segments Example 21.14 Code Protection and CodeGuard™ Security – Slave PRAM 22.0 Instruction Set Summary TABLE 22-1: Symbols Used in Opcode Descriptions TABLE 22-2: Instruction Set Overview 23.0 Development Support 24.0 Electrical Characteristics Absolute Maximum Ratings(1) 24.1 DC Characteristics TABLE 24-1: Operating MIPS vs. Voltage TABLE 24-2: Thermal Operating Conditions TABLE 24-3: Thermal Packaging Characteristics TABLE 24-4: Operating Voltage Specifications TABLE 24-5: DC Characteristics: Operating Current (Idd) (Master Run/Slave Run) TABLE 24-6: DC Characteristics: Operating Current (Idd) (Master Sleep/Slave Run) TABLE 24-7: DC Characteristics: Operating Current (Idd) (Master Run/Slave Sleep) TABLE 24-8: DC Characteristics: Operating Current (Iidle) (Master Idle/Slave Idle) TABLE 24-9: DC Characteristics: Idle Current (Iidle) (Master Idle/Slave Sleep) TABLE 24-10: DC Characteristics: Idle Current (Iidle) (Master Sleep/Slave Idle) TABLE 24-11: DC Characteristics: Power-Down Current (Ipd) TABLE 24-12: DC Characteristics: Watchdog Timer Delta Current (DIwdt)(1) TABLE 24-13: DC Characteristics: PWM Delta Current(1,2,3) TABLE 24-14: DC Characteristics: APLL Delta Current TABLE 24-15: DC Characteristics: ADC D Current TABLE 24-16: DC Characteristics: Comparator + DAC Delta Current TABLE 24-17: DC Characteristics: PGA Delta Current(1) TABLE 24-18: I/O Pin Input Specifications TABLE 24-19: I/O Pin Input Specifications TABLE 24-20: I/O Pin Input Injection Current Specifications TABLE 24-21: I/O Pin Output Specifications TABLE 24-22: Electrical Characteristics: BOR TABLE 24-23: Program Memory 24.2 AC Characteristics and Timing Parameters TABLE 24-24: Temperature and Voltage Specifications – AC FIGURE 24-1: Load Conditions for Device Timing Specifications TABLE 24-25: Capacitive Loading Requirements on Output Pins FIGURE 24-2: External Clock Timing TABLE 24-26: External Clock Timing Requirements TABLE 24-27: PLL Clock Timing Specifications TABLE 24-28: Auxiliary PLL Clock Timing Specifications TABLE 24-29: Internal FRC Accuracy TABLE 24-30: Internal LPRC Accuracy FIGURE 24-3: I/O Timing Characteristics TABLE 24-31: I/O Timing Requirements FIGURE 24-4: BOR and Master Clear Reset Timing Characteristics TABLE 24-32: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements FIGURE 24-5: High-Speed PWMx Module Fault Timing Characteristics FIGURE 24-6: High-Speed PWMx Module Timing Characteristics TABLE 24-33: High-Speed PWMx Module Timing Requirements TABLE 24-34: SPIx Maximum Data/Clock Rate Summary FIGURE 24-7: SPIx Master Mode (Half-Duplex, Transmit Only, CKE = 0) Timing Characteristics FIGURE 24-8: SPIx Master Mode (Half-Duplex, Transmit Only, CKE = 1) Timing Characteristics TABLE 24-35: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements FIGURE 24-9: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Characteristics TABLE 24-36: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements FIGURE 24-10: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Characteristics TABLE 24-37: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements FIGURE 24-11: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) Timing Characteristics TABLE 24-38: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) Timing Requirements FIGURE 24-12: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 0) Timing Characteristics TABLE 24-39: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 0) Timing Requirements FIGURE 24-13: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode) FIGURE 24-14: I2Cx Bus Data Timing Characteristics (Master Mode) TABLE 24-40: I2Cx Bus Data Timing Requirements (Master Mode) FIGURE 24-15: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode) FIGURE 24-16: I2Cx Bus Data Timing Characteristics (Slave Mode) TABLE 24-41: I2Cx Bus Data Timing Requirements (Slave Mode) FIGURE 24-17: UARTx Module I/O Timing Characteristics TABLE 24-42: UARTx Module I/O Timing Requirements Table 24-43: ADC Module Specifications Table 24-44: Analog-to-Digital Conversion Timing Specifications TABLE 24-45: High-Speed Analog Comparator Module Specifications TABLE 24-46: DACx Module Specifications TABLE 24-47: DACx Output (DACOUT1 Pin) Specifications TABLE 24-48: PGAx Module Specifications TABLE 24-49: Constant-Current Source Specifications 25.0 High-Temperature Electrical Characteristics Absolute Maximum Ratings(1) 25.1 DC Characteristics TABLE 25-1: Operating MIPS vs. Voltage TABLE 25-2: Thermal Operating Conditions TABLE 25-3: Thermal Packaging Characteristics(1) TABLE 25-4: Operating Voltage Specifications TABLE 25-5: DC CHARACTERISTICS: OPERATING CURRENT (Idd) (MASTER RUN/SLAVE RUN)(2) TABLE 25-6: DC Characteristics: Operating Current (Idd) (Master Sleep/Slave Run) TABLE 25-7: DC Characteristics: Operating Current (Idd) (Master Run/Slave Sleep) TABLE 25-8: DC CHARACTERISTICS: OPERATING CURRENT (Iidle) (MASTER IDLE/SLAVE IDLE)(2) TABLE 25-9: DC CHARACTERISTICS: IDLE CURRENT (Iidle) (MASTER IDLE/SLAVE SLEEP)(2) TABLE 25-10: DC CHARACTERISTICS: IDLE CURRENT (Iidle) (MASTER SLEEP/SLAVE IDLE)(2) TABLE 25-11: Power-Down Current (Ipd)(2) TABLE 25-12: Watchdog Timer Delta Current (DIwdt)(1) TABLE 25-13: PWM Delta Current(1) TABLE 25-14: APLL Delta Current TABLE 25-15: ADC Delta Current(1,2) TABLE 25-16: Comparator + DAC Delta Current TABLE 25-17: PGAx Delta Current(1) TABLE 25-18: I/O Pin Input Specifications TABLE 25-19: Internal FRC Accuracy TABLE 25-20: Internal LPRC Accuracy Table 25-21: ADC Module Specifications TABLE 25-22: DACx Module Specifications TABLE 25-23: PGAx Module Specifications 26.0 Packaging Information 26.1 Package Marking Information 26.1 Package Marking Information (Continued) 26.2 Package Details Appendix A: Revision History Revision A (August 2017) Revision B (June 2018) Revision C (November 2018) Revision C (Continued) Revision D (August 2019) INDEX The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service