Preliminary Datasheet QPC1252Q (Qorvo) - 10

PRELIMINARY QPC1252Q BROADBAND HIGH LINEARITY DSDA e-CALL ANTENNA ROUTING SWITCH Reg31 (0x1F) ─ MANUFACTURER_US_ID Bit(s) Field Name Description Reset B/G Trig R/W
Upper four bits of MIPI Manufacturer ID Note: This is a read-only register. However, as part of the special 7:4 MFG_ID[11:8] 0x3 No No R programming sequence for writing USID, a write command sequence is performed on this register, but does not update it. See MIPI 6.6.2 for details. Programmable Unique Slave ID 3:0 USID[3:0] 0xA No No R/W Note: USID is only writeable using a special programming sequence. See MIPI 6.6.2 for details.
Reg32 (0x20) ─ EXT_PRODUCT_ID Bit(s) Field Name Description Reset B/G Trig R/W
Upper eight bits of Product Number Note: These are read-only registers. However, as part of the special 7:0 EXT_PROD_ID[15:8] 0x00 No No R programming sequence for writing USID, a write command sequence is performed on one or both registers, but does not update them. See MIPI 6.6.2 for details.
Reg34 (0x22) ─ GROUP_ID2 Bit(s) Field Name Description Reset B/G Trig R/W
7:4 GSID0[3:0] Group Slave ID0 0x0 No No R/W 3:0 GSID1[3:0] Group Slave ID1 0x0 No No R/W
Reg35 (0x23) ─ UDR_RST Bit(s) Field Name Description Reset B/G Trig R/W
Setting this bit initiates a software reset 7 SW_RESET[7] 0 B/G No R/W Note: On software reset, this register and all User Defined registers (UDRs) are reset. This bit will always read as 0. 6:0 RESERVED 0x00 No No R/W QPC1252Q Preliminary DS RevA | Subject to change without notice 10 of 17
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