Datasheet 2ED24427N01F (Infineon) - 10
| 制造商 | Infineon |
| 描述 | 10 A dual -channel low-side gate driver IC |
| 页数 / 页 | 21 / 10 — 2ED24427N01F. 10 A dual-channel low-side gate driver IC. Figure 6. Bridge … |
| 修订版 | 02_00 |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
2ED24427N01F. 10 A dual-channel low-side gate driver IC. Figure 6. Bridge Tied Gate Driver waveforms
该数据表的模型线
文件文字版本
2ED24427N01F 10 A dual-channel low-side gate driver IC Figure 6 Bridge Tied Gate Driver waveforms
The waveforms in Figure 6 show that: The lower LLK is, the lower and shorter is the ringing on the Fets gate voltage, particular care must be paid to guarantee that the max Vgs voltage of the Fet is not exceeded during operation. The lower LLK is, the shorter the propagation delay is from the driver to the gate of the Fet and the higher the peak current is into its gate. The higher Lm is, the lower ILM is; at the primary side the gate peak current, summed to ILM, constitute the total current flowing out of the gate driver. Datasheet 10 of 21 V 2.0 www.infineon.com/gdLowSide 2019-11-10
The waveforms in Figure 6 show that: The lower LLK is, the lower and shorter is the ringing on the Fets gate voltage, particular care must be paid to guarantee that the max Vgs voltage of the Fet is not exceeded during operation. The lower LLK is, the shorter the propagation delay is from the driver to the gate of the Fet and the higher the peak current is into its gate. The higher Lm is, the lower ILM is; at the primary side the gate peak current, summed to ILM, constitute the total current flowing out of the gate driver. Datasheet 10 of 21 V 2.0 www.infineon.com/gdLowSide 2019-11-10