Datasheet LTC4332 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | SPI Extender Over Rugged Differential Link |
| 页数 / 页 | 22 / 4 — SWITCHING CHARACTERISTICS. The. denotes the specifications which apply … |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
SWITCHING CHARACTERISTICS. The. denotes the specifications which apply over the full operating
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SWITCHING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, GND = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Local Mode (REMOTE = 0)
fSCK:SLAVE SCK Input Frequency (SPEED INDEX = 8) (Table 2) l 2000 kHz 10 kHz tSCKH:SLAVE SCK Input High Time (Figure 7) l 100 ns tSCKL:SLAVE SCK Input Low Time l 100 ns tBUF:SLAVE SSx Rise to SSx Fall Delay (Note 3) l 2 • SF µs tSSFSCK:SLAVE SSx Fall to SCK Rise Delay (Note 3) l 2 • SF 168000 µs tSCKRSS:SLAVE SCK Rise to SSx Rise Delay (Note 3) l 1 • SF 168000 µs tDMISO:SLAVE MISO Data Valid from SCK Fall Delay CL = 20pF l 100 ns tHMISO:SLAVE MISO Data Remains Valid from SCK Fall Delay CL = 20pF l 40 ns tSMOSI:SLAVE MOSI Data Setup to SCK Rise l 40 ns tHMOSI:SLAVE MOSI Data Hold after SCK Rise l 40 ns
Remote Mode (REMOTE = 1)
tSCKL:MASTER SCK Low from LTC4332 (CPOL, CPHA) = (0,0) or (1,1) l 0.2 • SF 0.3 • SF µs (Figure 9) (Note 4) tSCKH:MASTER SCK High from LTC4332 (CPOL, CPHA) = (0,1) or (1,0) l 0.15 • SF 0.3 • SF µs (Note 4) tSCKTSS:MASTER SCK Trailing Edge to SSx High (Note 4) l 0.2 • SF µs tSCKJ:MASTER SCK Cycle to Cycle Jitter (Figure 8) l ±30 ns tDMOSI:MASTER MOSI Data Valid from SCK Fall Delay CL = 20pF l 15 ns tHMOSI:MASTER MOSI Data Remains Valid from SCK Fall Delay CL = 20pF l –5 ns tSMISO:MASTER MISO Data Setup to SCK Rise l 40 ns tHMISO:MASTER MISO Data Hold after SCK Rise l 40 ns tTIMEOUT:MASTER Active Slave Select Timeout l 148 175 ms
Link Interface
tRD, tFD Differential Driver Rise or Fall Time RDIFF = 54Ω, CL = 100pF l 4 15 ns tLINK_TIMEOUT Response Time for LINK Release after Disconnection REMOTE = 1 168 ms REMOTE = 0 100 µs
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
All currents into device pins are positive; all currents out of device may cause permanent damage to the device. Exposure to any Absolute are negative. All voltages are referenced to their corresponding ground Maximum Rating condition for extended periods may affect device unless otherwise specified. reliability and lifetime.
Note 6:
Continuous operation above specified maximum operating
Note 2:
Guaranteed by design, not production tested. junction temperature may result in device degradation or failure.
Note 3:
SF = Speed Factor. See Table 2.
Note 7:
Link network with RB = 250Ω, RDIFF = 100Ω, and CL = 150pF from
Note 4:
CPOL and CPHA set using fields REM_SSx_POL and REM_SSx_ Figure 4 unless otherwise noted. PHA in the CONFIG register. Rev. A 4 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Switching Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuits Timing Diagram Applications Information Package Description Typical Application Related Parts
SWITCHING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, GND = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Local Mode (REMOTE = 0)
fSCK:SLAVE SCK Input Frequency (SPEED INDEX = 8) (Table 2) l 2000 kHz 10 kHz tSCKH:SLAVE SCK Input High Time (Figure 7) l 100 ns tSCKL:SLAVE SCK Input Low Time l 100 ns tBUF:SLAVE SSx Rise to SSx Fall Delay (Note 3) l 2 • SF µs tSSFSCK:SLAVE SSx Fall to SCK Rise Delay (Note 3) l 2 • SF 168000 µs tSCKRSS:SLAVE SCK Rise to SSx Rise Delay (Note 3) l 1 • SF 168000 µs tDMISO:SLAVE MISO Data Valid from SCK Fall Delay CL = 20pF l 100 ns tHMISO:SLAVE MISO Data Remains Valid from SCK Fall Delay CL = 20pF l 40 ns tSMOSI:SLAVE MOSI Data Setup to SCK Rise l 40 ns tHMOSI:SLAVE MOSI Data Hold after SCK Rise l 40 ns
Remote Mode (REMOTE = 1)
tSCKL:MASTER SCK Low from LTC4332 (CPOL, CPHA) = (0,0) or (1,1) l 0.2 • SF 0.3 • SF µs (Figure 9) (Note 4) tSCKH:MASTER SCK High from LTC4332 (CPOL, CPHA) = (0,1) or (1,0) l 0.15 • SF 0.3 • SF µs (Note 4) tSCKTSS:MASTER SCK Trailing Edge to SSx High (Note 4) l 0.2 • SF µs tSCKJ:MASTER SCK Cycle to Cycle Jitter (Figure 8) l ±30 ns tDMOSI:MASTER MOSI Data Valid from SCK Fall Delay CL = 20pF l 15 ns tHMOSI:MASTER MOSI Data Remains Valid from SCK Fall Delay CL = 20pF l –5 ns tSMISO:MASTER MISO Data Setup to SCK Rise l 40 ns tHMISO:MASTER MISO Data Hold after SCK Rise l 40 ns tTIMEOUT:MASTER Active Slave Select Timeout l 148 175 ms
Link Interface
tRD, tFD Differential Driver Rise or Fall Time RDIFF = 54Ω, CL = 100pF l 4 15 ns tLINK_TIMEOUT Response Time for LINK Release after Disconnection REMOTE = 1 168 ms REMOTE = 0 100 µs
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
All currents into device pins are positive; all currents out of device may cause permanent damage to the device. Exposure to any Absolute are negative. All voltages are referenced to their corresponding ground Maximum Rating condition for extended periods may affect device unless otherwise specified. reliability and lifetime.
Note 6:
Continuous operation above specified maximum operating
Note 2:
Guaranteed by design, not production tested. junction temperature may result in device degradation or failure.
Note 3:
SF = Speed Factor. See Table 2.
Note 7:
Link network with RB = 250Ω, RDIFF = 100Ω, and CL = 150pF from
Note 4:
CPOL and CPHA set using fields REM_SSx_POL and REM_SSx_ Figure 4 unless otherwise noted. PHA in the CONFIG register. Rev. A 4 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Switching Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuits Timing Diagram Applications Information Package Description Typical Application Related Parts