Datasheet IMD111T-6F040, IMD112T-6F040 (Infineon) - 6

制造商Infineon
描述Smart driver for motor control. Motor controller with integrated high-voltage gate driver
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iMOTION™ IMD111T/IMD112T - Smart driver for motor control. Motor controller with integrated high-voltage gate driver

iMOTION™ IMD111T/IMD112T - Smart driver for motor control Motor controller with integrated high-voltage gate driver

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iMOTION™ IMD111T/IMD112T - Smart driver for motor control Motor controller with integrated high-voltage gate driver 2 Pin configuration 2 Pin configuration
The pin type is specified as follows: • I - digital input • O - digital output • AIN - analog input • P - power
Figure 3
shows the pad structure and pin function control configuration for the input and output pins. The pin function, type and pull up/pull down circuit configuration are all controlled by the Motion Control Engine. Digital input, output or analog input signals that are not assigned to MCE functions can be assigned to the script engine. The gate driver outputs are controlled by MCE PWM signals internally connected to the gate driver inputs. Pin control logic VDD
Pad
VDD I
Pn.y
Pin function O multiplexer GND GND
ESD
AIN
Figure 3 Pin Pad and Function Configuration
The pin function table given below refers to the standard configuration. The pin control or interface functions are defined by the version of software downloaded to the device and may change. Some of the input pins can be configured to have pull up or pull down resistor and some output pins can be configured to push-pull or open drain. This is described in the respective software reference manual. Pins can serve multiple functions and have to be configured accordingly. Please also refer to the respective pin configuration drawings in this data sheet and the description in the MCE software reference manual. Pins that do not have any signal assigned are reserved for future use. These pins should be left unconnected and neither be connected to ground nor to the positive supply. Note: All required reference voltages are generated by an internal DAC, therefore the pins like REFU, REFV, and REFW only require a blocking capacitor.
2.1 Pin definitions and functions Table 1 Pin definitions and functions Signal Type IMD111T IMD112T Description Supply
VCC1 Power 8 8 Control supply voltage input to the voltage regulator VCC Power 22 22 Gate drive supply voltage VDD Power 5 5 Digital controller voltage (this 5V LDO output must be blocked with a ceramic capacitor) VSS Power 6, 7, 23 6, 7, 23 Ground Datasheet 6 1.0 2020-12-4 Document Outline Features Potential applications Product validation Description Table of contents 1 Block diagram reference 2 Pin configuration 2.1 Pin definitions and functions 2.2 Pin configuration drawing IMD111T 2.3 Pin configuration drawing IMD112T 3 Functional description 3.1 Overview 3.2 Motion Control Engine 3.3 Gate Driver 3.4 Low Side Supply (VCC, VSS and COM) 3.5 High Side Supplies (VB1,2,3 and VS1,2,3) 3.6 Low and High Side Outputs (LO1,2,3 and HO1,2,3) 3.7 Internal Voltage Regulator 3.8 Application diagrams 4 Electrical characteristics and parameters 4.1 General parameters 4.1.1 Parameter Interpretation 4.1.2 Absolute maximum ratings 4.1.3 Pin Reliability in Overload 4.1.4 Operating Conditions 4.2 DC characteristics 4.2.1 Input/Output Characteristics 4.2.2 Analog to Digital Converter (ADC) 4.2.3 Analog comparator characteristics 4.2.4 Power Supply Current 4.2.5 Flash Memory Parameters 4.2.6 Static parameters gate driver 4.2.7 Static parameters voltage regulator 4.3 AC characteristics 4.3.1 Testing Waveforms 4.3.2 On-Chip Oscillator Characteristics 4.3.3 Dynamic parameters gate driver 4.3.4 Timing diagrams 4.4 Motor Control Parameters 4.4.1 PWM Characteristics 4.4.2 Current Sensing 4.4.3 Fault Timing 4.5 Power Factor Correction (PFC) parameters 4.5.1 Boost PFC characteristics 4.5.2 Totem Pole PFC characteristics 4.5.3 PFC Current Sensing 4.6 Control Interface Parameters 4.6.1 Control Input Interfaces 4.6.2 Serial Interface Parameters 4.6.2.1 UART Interface 4.6.3 Over Temperature Input 4.6.4 Pulse Output 5 Device and package specifications 5.1 Quality declaration 5.2 SBSL and Chip-IDs 5.3 Thermal considerations 5.4 Package Outline PG-LQFP-40-1 5.5 Part marking information Revision history Disclaimer