Datasheet LTC7801 (Analog Devices) - 9

制造商Analog Devices
描述150V Low IQ, Synchronous Step-Down DC/DC Controller
页数 / 页38 / 9 — PIN FUNCTIONS (QFN/TSSOP) VFB (Pin 1/Pin 3):. FREQ (Pin 8/Pin 10):. ITH …
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PIN FUNCTIONS (QFN/TSSOP) VFB (Pin 1/Pin 3):. FREQ (Pin 8/Pin 10):. ITH (Pin 2/Pin 4):. MODE (Pin 3/Pin 5):

PIN FUNCTIONS (QFN/TSSOP) VFB (Pin 1/Pin 3): FREQ (Pin 8/Pin 10): ITH (Pin 2/Pin 4): MODE (Pin 3/Pin 5):

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PIN FUNCTIONS (QFN/TSSOP) VFB (Pin 1/Pin 3):
Feedback Input. This pin receives the
FREQ (Pin 8/Pin 10):
Frequency Control Pin for the remotely sensed feedback voltage from an external resis- Internal VCO. Connecting the pin to GND forces the VCO tor divider across the output. to a fixed low frequency of 350kHz. Connecting the pin
ITH (Pin 2/Pin 4):
Error Amplifier Output and Switching to INTVCC forces the VCO to a fixed high frequency of Regulator Compensation Point. The current comparator 535kHz. Other frequencies between 50kHz and 900kHz trip point increases with this control voltage. can be programmed by using a resistor between FREQ and GND. An internal 20µA pull-up current develops the
MODE (Pin 3/Pin 5):
Mode Select and Burst Clamp Adjust voltage to be used by the VCO to control the frequency. Input. This input determines how the LTC7801 operates at light loads. Pulling this pin to ground selects Burst Mode
DRVSET (Pin 9/Pin 11):
DRVCC Regulation Program Pin. operation with the burst clamp level defaulting to 25% of This pin sets the regulated output voltage of the DRVCC V linear regulator. Tying this pin to GND sets DRVCC to 6.0V. SENSE(MAX). Tying this pin to a voltage between 0.5V and 1.0V selects Burst Mode operation and adjusts the burst Tying this pin to INTVCC sets DRVCC to 10V. Other volt- clamp between 10% and 60%. Tying this pin to INTV ages between 5V and 10V can be programmed by placing CC forces continuous inductor current operation. Tying this a resistor (50k to 100k) between the DRVSET pin and pin to a voltage greater than 1.4V and less than INTV GND. An internal 20µA pull-up current develops the volt- CC – 1.3V selects pulse-skipping operation. age to be used as the reference to the DRVCC LDO. See PC Board Layout Checklist in the Applications Information
GND (Pin 4, Exposed Pin 25/Pin 6, Exposed Pad Pin 25):
section for additional considerations when using higher Ground. All GND pins must be tied together for operation. DRVSET settings. The exposed pad must be soldered to PCB ground for rated electrical and thermal performance.
DRVUV (Pin 10/Pin 12):
DRVCC UVLO Program Pin. This pin determines the higher or lower DRVCC UVLO and
CPUMP_EN (Pin 5/Pin 7):
Charge Pump Enable Pin for EXTVCC switchover thresholds, as listed on the Electrical the Top Gate Driver Boost Supply. Tying this pin to INTVCC Characteristics table. Connecting DRVUV to GND chooses enables the boost supply charge pump and allows for the lower thresholds whereas tying DRVUV to INTVCC 100% duty cycle operation in dropout. Tying this pin to chooses the higher thresholds. Do not float this pin. GND disables the charge pump and enables boost refresh, allowing for 99% duty cycle operation in dropout. Do not
TG (Pin 11/Pin 13):
High Current Gate Drives for Top float this pin. N-Channel MOSFET. This is the output of floating high side driver with a voltage swing equal to DRVCC superimposed
PLLIN (Pin 6/ Pin 8):
External Synchronization Input to on the switch node voltage SW. Phase Detector. When an external clock is applied to this pin, the phase-locked loop will force the rising TG signal
SW (Pin 12/Pin 14):
Switch Node Connection to Inductor. to be synchronized with the rising edge of the external
BOOST (Pin 13/Pin 15):
Bootstrapped Supply to the clock. If the MODE pin is set to Forced Continuous Mode Topside Floating Driver. A capacitor is connected between or Burst Mode operation, then the regulator operates the BOOST and SW pins. Voltage swing at the BOOST pin in Forced Continuous Mode when synchronized. If the is from approximately DRVCC to (VIN + DRVCC). MODE pin is set to pulse-skipping mode, then the regula-
BG (Pin 14/Pin 16):
High Current Gate Drive for Bottom tor operates in pulse-skipping mode when synchronized. (Synchronous) N-Channel MOSFET. Voltage swing at this
PGOOD (Pin 7/Pin 9):
Open-Drain Logic Output. PGOOD pin is from ground to DRVCC. is pulled to ground when the voltage on the VFB pin is not within ±10% of its set point. Rev. A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts