Datasheet AD744 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | Precision, 500 ns Settling BiFET Op Amp |
| 页数 / 页 | 15 / 9 — AD744. Table II. Recommended Values of CCOMP vs. Various Load Conditions … |
| 修订版 | D |
| 文件格式/大小 | PDF / 516 Kb |
| 文件语言 | 英语 |
AD744. Table II. Recommended Values of CCOMP vs. Various Load Conditions for the Circuits of Figures 31 and 32. Max. Slew
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AD744 Table II. Recommended Values of CCOMP vs. Various Load Conditions for the Circuits of Figures 31 and 32. Max Slew –3 dB R1 R2 Gain Gain CLOAD CCOMP CLEAD Rate Bandwidth (
⍀
) (
⍀
) Follower Inverter (pF) (pF) (pF) (V/
s) (MHz)
4.99 k 4.99 k 2 1 50 0 7 75 2.51 4.99 k 4.99 k 2 1 150 5 7 37 2.31 4.99 k 4.99 k 2 1 1000 20 – 14 1.2 4.99 k 4.99 k 2 1 >2000 25 – 12.52 1.0 499 Ω 4.99 k 11 10 270 0 – 75 1.2 499 Ω 4.99 k 11 10 390 2 – 50 0.85 499 Ω 4.99 k 11 10 1000 5 – 372 0.60 NOTES 1Bandwidth with CLEAD adjusted for minimum settling time. 2Into large capacitive loads the AD744’s 25 mA output current limit sets the slew rate of the amplifier, in V/ µs, equal to 0.025 amps divided by the value of CLOAD in µF. Slew rate is specified into rated max CLOAD except for cases marked 2, which are specified with a 50 pF. load.
CLEAD*
Due to manufacturing variations in the value of the internal
R2*
CCOMP, it is recommended that the amplifier’s response be
+V
optimized for the desired gain by using a 2 to 10 pF trimmer
S
capacitor rather than using a fixed value.
1
F 0.1
F R1* VIN R1* R2* AD744 VOUT +VS OPTIONAL 1
F 0.1
F CCOMP 1
F 0.1
F AD744 VOUT *SEE TABLE II –VS NOT CONNECTED
\
VIN
Figure 32. AD744 Connected as an Inverting Amplifier
2 – 10pF
Operating at Gains of 1 or Greater
*SEE TABLE III 1
F 0.1
F –VS Using Decompensation to Extend the Gain Bandwidth Product
Figure 33. Using the Decompensation Connection to When the AD744 is used in applications where the closed-loop Extend Gain Bandwidth gain is greater than 10, gain bandwidth product may be enhanced by connecting a small capacitor between Pins 1 and 5 (Figure 33). At low frequencies, this capacitor cancels the effects of the
Table III. Performance Summary for the Circuit of Figure 33
chip’s internal compensation capacitor, CCOMP, effectively dec-
R1 R2 Gain Gain –3 dB Gain/BW
ompensating the amplifier.
(
⍀
) (
⍀
) Follower Inverter Bandwidth Product
1 k 10 k 11 10 2.5 MHz 25 MHz 100 10 k 101 100 760 kHz 76 MHz 100 100 k 1001 1000 225 kHz 225 MHz REV. D –9– Document Outline FEATURES ac Performance dc Performance APPLICATIONS CONNECTION DIAGRAMS PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS METALIZATION PHOTOGRAPH TYPICAL CHARACTERISITICS POWER SUPPLY BYPASSING MEASURING AD744 SETTLING TIME EXTERNAL FREQUENCY COMPENSATION Using Decompensation to Extend the Gain Bandwidth Product HIGH-SPEED OP AMP APPLICATIONS TECHNIQUES DAC Buffers (I-to-V Converters) A HIGH-SPEED, 3 OP AMP INSTRUMENTATION AMPLIFIER CIRCUIT Minimizing Settling Time in Real-World Applications OUTLINE DIMENSIONS ORDERING GUIDE REVISION HISTORY
⍀
) (
⍀
) Follower Inverter (pF) (pF) (pF) (V/
s) (MHz)
4.99 k 4.99 k 2 1 50 0 7 75 2.51 4.99 k 4.99 k 2 1 150 5 7 37 2.31 4.99 k 4.99 k 2 1 1000 20 – 14 1.2 4.99 k 4.99 k 2 1 >2000 25 – 12.52 1.0 499 Ω 4.99 k 11 10 270 0 – 75 1.2 499 Ω 4.99 k 11 10 390 2 – 50 0.85 499 Ω 4.99 k 11 10 1000 5 – 372 0.60 NOTES 1Bandwidth with CLEAD adjusted for minimum settling time. 2Into large capacitive loads the AD744’s 25 mA output current limit sets the slew rate of the amplifier, in V/ µs, equal to 0.025 amps divided by the value of CLOAD in µF. Slew rate is specified into rated max CLOAD except for cases marked 2, which are specified with a 50 pF. load.
CLEAD*
Due to manufacturing variations in the value of the internal
R2*
CCOMP, it is recommended that the amplifier’s response be
+V
optimized for the desired gain by using a 2 to 10 pF trimmer
S
capacitor rather than using a fixed value.
1
F 0.1
F R1* VIN R1* R2* AD744 VOUT +VS OPTIONAL 1
F 0.1
F CCOMP 1
F 0.1
F AD744 VOUT *SEE TABLE II –VS NOT CONNECTED
\
VIN
Figure 32. AD744 Connected as an Inverting Amplifier
2 – 10pF
Operating at Gains of 1 or Greater
*SEE TABLE III 1
F 0.1
F –VS Using Decompensation to Extend the Gain Bandwidth Product
Figure 33. Using the Decompensation Connection to When the AD744 is used in applications where the closed-loop Extend Gain Bandwidth gain is greater than 10, gain bandwidth product may be enhanced by connecting a small capacitor between Pins 1 and 5 (Figure 33). At low frequencies, this capacitor cancels the effects of the
Table III. Performance Summary for the Circuit of Figure 33
chip’s internal compensation capacitor, CCOMP, effectively dec-
R1 R2 Gain Gain –3 dB Gain/BW
ompensating the amplifier.
(
⍀
) (
⍀
) Follower Inverter Bandwidth Product
1 k 10 k 11 10 2.5 MHz 25 MHz 100 10 k 101 100 760 kHz 76 MHz 100 100 k 1001 1000 225 kHz 225 MHz REV. D –9– Document Outline FEATURES ac Performance dc Performance APPLICATIONS CONNECTION DIAGRAMS PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS METALIZATION PHOTOGRAPH TYPICAL CHARACTERISITICS POWER SUPPLY BYPASSING MEASURING AD744 SETTLING TIME EXTERNAL FREQUENCY COMPENSATION Using Decompensation to Extend the Gain Bandwidth Product HIGH-SPEED OP AMP APPLICATIONS TECHNIQUES DAC Buffers (I-to-V Converters) A HIGH-SPEED, 3 OP AMP INSTRUMENTATION AMPLIFIER CIRCUIT Minimizing Settling Time in Real-World Applications OUTLINE DIMENSIONS ORDERING GUIDE REVISION HISTORY