Datasheet ADL8111 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 10 MHz to 8000 MHz Bypass Amplifier |
| 页数 / 页 | 24 / 4 — ADL8111. Data Sheet. Table 2. Parameter. Test Conditions/Comments. Min. … |
| 文件格式/大小 | PDF / 811 Kb |
| 文件语言 | 英语 |
ADL8111. Data Sheet. Table 2. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit. Table 3. Total Supply Current by VDD Parameter
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ADL8111 Data Sheet
VDD_PA = +5 V, IDQ_PA = 70 mA, VSS_SW = −3.3 V, VDD_SW = +3.3 V, and TA = 25°C, unless otherwise noted.
Table 2. Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL FUNCTION Frequency Range 5000 8000 MHz INTERNAL AMPLIFIER STATE Small Signal Gain 10.6 11.5 dB Gain Flatness ±1 dB Input Return Loss 14 dB Output Return Loss 16 dB P1dB 17 dBm OIP3 32 dBm Noise Figure 4.5 dB VDD_PA 3.0 5.0 5.5 V INTERNAL BYPASS SWITCH STATE Insertion Loss 2.7 dB IIP31 58 dBm P0.5dB 34 dBm Return Loss On State 18 dB Return Loss Off State 22 dB VDD_SW 3.0 3.3 3.6 V VSS_SW −3.6 −3.3 −3.0 V EXTERNAL BYPASS A AND EXTERNAL BYPASS B STATES2 Insertion Loss 1.5 dB IIP3 57.5 dBm P0.5dB 34.5 dBm Return Loss On State 17 dB Return Loss Off State 20 dB VDD_SW 3.0 3.3 3.6 V VSS_SW −3.6 −3.3 −3.0 V 1 IIP3 and compression data for the internal bypass and the External Bypass B states is the same as the External Bypass A state data. 2 External Bypass A and External Bypass B were tested with an external 50 Ω transmission line on the evaluation board.
Table 3. Total Supply Current by VDD Parameter Min Typ Max Unit
Supply Current VDD_PA = 5 V 70 mA VDD_SW = +3.3 V 30 μA VSS_SW = −3.3 V 30 μA
Table 4. Logic Control Voltage Digital Control Inputs Min Typ Max Unit Current
Low 0 0.8 V <1 μA typical High 1.4 VDD_SW + 0.3 V <1 μA typical Rev. 0 | Page 4 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL BYPASS A STATE INTERNAL AMPLIFIER STATE INTERNAL BYPASS STATE EXTERNAL BYPASS B STATE TEST CIRCUITS THEORY OF OPERATION SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down EVALUATION PCB EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE
VDD_PA = +5 V, IDQ_PA = 70 mA, VSS_SW = −3.3 V, VDD_SW = +3.3 V, and TA = 25°C, unless otherwise noted.
Table 2. Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL FUNCTION Frequency Range 5000 8000 MHz INTERNAL AMPLIFIER STATE Small Signal Gain 10.6 11.5 dB Gain Flatness ±1 dB Input Return Loss 14 dB Output Return Loss 16 dB P1dB 17 dBm OIP3 32 dBm Noise Figure 4.5 dB VDD_PA 3.0 5.0 5.5 V INTERNAL BYPASS SWITCH STATE Insertion Loss 2.7 dB IIP31 58 dBm P0.5dB 34 dBm Return Loss On State 18 dB Return Loss Off State 22 dB VDD_SW 3.0 3.3 3.6 V VSS_SW −3.6 −3.3 −3.0 V EXTERNAL BYPASS A AND EXTERNAL BYPASS B STATES2 Insertion Loss 1.5 dB IIP3 57.5 dBm P0.5dB 34.5 dBm Return Loss On State 17 dB Return Loss Off State 20 dB VDD_SW 3.0 3.3 3.6 V VSS_SW −3.6 −3.3 −3.0 V 1 IIP3 and compression data for the internal bypass and the External Bypass B states is the same as the External Bypass A state data. 2 External Bypass A and External Bypass B were tested with an external 50 Ω transmission line on the evaluation board.
Table 3. Total Supply Current by VDD Parameter Min Typ Max Unit
Supply Current VDD_PA = 5 V 70 mA VDD_SW = +3.3 V 30 μA VSS_SW = −3.3 V 30 μA
Table 4. Logic Control Voltage Digital Control Inputs Min Typ Max Unit Current
Low 0 0.8 V <1 μA typical High 1.4 VDD_SW + 0.3 V <1 μA typical Rev. 0 | Page 4 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL BYPASS A STATE INTERNAL AMPLIFIER STATE INTERNAL BYPASS STATE EXTERNAL BYPASS B STATE TEST CIRCUITS THEORY OF OPERATION SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down EVALUATION PCB EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE