Datasheet ADL9005 (Analog Devices) - 6

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ADL9005 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DD2V4/ 3 ACG ACG NC NC NC NC 24 23 22 21 20 19 R 1 18 BIAS NC NC 2 17 GND GND 3 ADL9005 16 RFOUT/VDD TOP VIEW RF 4 15 IN GND (Not to Scale) GND 5 14 NC NC 6 13 NC 7 8 9 10 11 12 1 2 NC NC NC NC ACG ACG NOTES 1. NC = NO INTERNAL CONNECTION. NOTE THE DATA SHOWN HEREIN WAS MEASURED WITH THESE PINS EXTERNALLY CONNECTED TO THE RF AND DC GROUND.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND.
25033- Figure 2. Pin Configuration
Table 8. Pin Function Descriptions Pin No. Mnemonic Description
1 RBIAS Current Mirror Bias Resistor Pin. Use the RBIAS pin to set the IDQ by connecting an external bias resistor as defined in Table 9. Refer to Figure 74 for the bias resistor connection. See Figure 3 for the interface schematic. 2, 6 to 10, 13, 14, 18 to 22 NC No Internal Connection. Note the data shown herein was measured with these pins externally connected to the RF and dc ground. 3, 5, 15, 17 GND Ground. The GND pins must be connected to RF and dc ground. See Figure 4 for the interface schematic. 4 RFIN RF Input. The RFIN pin is dc-coupled and matched to 50 Ω. See Figure 5 for the interface schematic. 11 ACG1 AC Grounding 1. A capacitor is required on the ACG1 pin to provide low frequency decoupling. Refer to Figure 74 for the capacitor value. See Figure 5 for the interface schematic. 12 ACG2 AC Grounding 2. A capacitor is required on the ACG2 pin to provide low frequency decoupling. Refer to Figure 74 for the capacitor value. See Figure 5 for the interface schematic. 16 RFOUT/VDD RF Output (RFOUT)/Drain Voltage for Amplifier (VDD). The RFOUT/VDD pin is dc-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. 23 ACG3 AC Grounding 3. A capacitor is required on the ACG3 pin to provide low frequency decoupling. Refer to Figure 74 for the capacitor value. See Figure 6 for the interface schematic. 24 ACG4/VDD2 AC Grounding 4 (ACG4). A capacitor is required on the ACG4 pin to provide low frequency decoupling. Refer to Figure 74 for the capacitor value. See Figure 6 for the interface schematic. Optional Drain Voltage for the Amplifier that Requires a Higher Voltage (VDD2). Do not use the VDD2 pin simultaneously with RFOUT/VDD. See Figure 6 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground. Rev. 0 | Page 6 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 0.01 GHz TO 14 GHz 14 GHz TO 20 GHz 20 GHz TO 26.5 GHz DC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings for ADL9005 ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS BIASING THROUGH THE ACG4/VDD2 PIN THEORY OF OPERATION APPLICATIONS INFORMATION BASIC CONNECTIONS BIASING THE ADL9005 BY USING THE LTM8020 PROVIDING DRAIN BIAS PROVIDING DRAIN BIAS THROUGH THE ACG4/VDD2 PIN POWER-UP AND POWER-DOWN SEQUENCING OUTLINE DIMENSIONS ORDERING GUIDE