Datasheet HMC8410 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 0.01 GHz to 10 GHz, GaAs, pHEMT, MMIC, Low Noise Amplifier |
| 页数 / 页 | 17 / 6 — HMC8410. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GND 1. … |
| 修订版 | D |
| 文件格式/大小 | PDF / 684 Kb |
| 文件语言 | 英语 |
HMC8410. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GND 1. NIC. RFIN/V. GG1. RFOUT/VDD. TOP VIEW. (Not to Scale)
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HMC8410 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 6 NIC HMC8410 RFIN/V 2 5 GG1 RFOUT/VDD TOP VIEW (Not to Scale) 3 4 NIC NIC NOTES 1. NIC = NOT INTERNALLY CONNECTED. THIS PIN MUST BE CONNECTED TO THE RF/DC GROUND.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND.
14657- Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 GND Ground. This pin must be connected to the RF/dc ground. See Figure 3 for the interface schematic. 2 RFIN/VGG1 RF Input (RFIN). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic. Gate Bias of the Amplifier (VGG1). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic. 3, 4, 6 NIC Not Internally Connected. This pin must be connected to the RF/dc ground. 5 RFOUT/VDD RF Output (RFOUT). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface schematic. Drain Bias for Amplifier (VDD). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS RFOUT/VDD GND
003 005 14657- 14657- Figure 3. GND Interface Schematic Figure 5. RFOUT/VDD Interface Schematic
RFIN/VGG1
004 14657- Figure 4. RFIN/VGG1 Interface Schematic Rev. D | Page 6 of 17 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY ELECTRICAL SPECIFICATIONS 0.01 GHz TO 3 GHz FREQUENCY RANGE 3 GHz TO 8 GHz FREQUENCY RANGE 8 GHz TO 10 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down TYPICAL APPLICATION CIRCUIT EVALUATION BOARD EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE
HMC8410 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 6 NIC HMC8410 RFIN/V 2 5 GG1 RFOUT/VDD TOP VIEW (Not to Scale) 3 4 NIC NIC NOTES 1. NIC = NOT INTERNALLY CONNECTED. THIS PIN MUST BE CONNECTED TO THE RF/DC GROUND.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND.
14657- Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 GND Ground. This pin must be connected to the RF/dc ground. See Figure 3 for the interface schematic. 2 RFIN/VGG1 RF Input (RFIN). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic. Gate Bias of the Amplifier (VGG1). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic. 3, 4, 6 NIC Not Internally Connected. This pin must be connected to the RF/dc ground. 5 RFOUT/VDD RF Output (RFOUT). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface schematic. Drain Bias for Amplifier (VDD). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS RFOUT/VDD GND
003 005 14657- 14657- Figure 3. GND Interface Schematic Figure 5. RFOUT/VDD Interface Schematic
RFIN/VGG1
004 14657- Figure 4. RFIN/VGG1 Interface Schematic Rev. D | Page 6 of 17 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY ELECTRICAL SPECIFICATIONS 0.01 GHz TO 3 GHz FREQUENCY RANGE 3 GHz TO 8 GHz FREQUENCY RANGE 8 GHz TO 10 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down TYPICAL APPLICATION CIRCUIT EVALUATION BOARD EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE