Datasheet ADPA7006 (Analog Devices) - 6

ADPA7006 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS UT EF O ET ND ND VR G RF G VD 16 15 14 13 12 V 1 DD3 11 VDD4 ADPA7006 V 2 DD1 10 TOP VIEW VDD2 V (Not to Scale) 3 GG1 9 VGG1 4 5 6 7 8 C C NI ND FIN ND NI G R G NOTES 1. NIC = NO INTERNAL CONNECTION. THESE PINS HAVE NO INTERNAL CONNECTIONS. 2. EXPOSED PAD. THE EXPOSED PAD MUST
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BE CONNECTED TO THE RF AND DC GROUND PLANE.
21027- Figure 2. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1, 11 VDD3, VDD4 Drain Bias for the Output Stage. External bypass capacitors are required. 2, 10 VDD1, VDD2 Drain Bias for the Driver Stage. External bypass capacitors are required. 3, 9 VGG1 Gate Bias Controls. External bypass capacitors are required. 4, 8 NIC No Internal Connection. These pins have no internal connections. 5, 7, 13, 15 GND Ground. These pins must be connected to RF and dc ground. 6 RFIN Radio Frequency Signal Input. This pin is ac-coupled and matched to 50 Ω. 12 VDET Detector Diode to Measure RF Output Power. Output power detection via this pin requires the application of a dc bias voltage through an external series resistor. Used in combination with the VREF pin, the difference voltage (VREF − VDET) is a temperature compensated dc voltage that is proportional to the RF output power. 14 RFOUT RF Signal Output. This pin is ac-coupled and matched to 50 Ω. 16 VREF Reference Diode Used for Temperature Compensation of VDET RF Output Power Measurements. Used in combination with VDET, this voltage provides temperature compensation to the VDET RF output power measurements. EPAD Exposed Pad. The exposed pad must be connected to the RF and dc ground plane. Rev. 0 | Page 6 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 18 GHz TO 24 GHz FREQUENCY RANGE 20 GHz TO 24 GHz FREQUENCY RANGE 24 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS CONSTANT IDD OPERATION THEORY OF OPERATION APPLICATIONS INFORMATION BIASING PROCEDURES BIASING THE ADPA7006 WITH THE HMC980LP4E APPLICATION CIRCUIT SETUP LIMITING VGATE AND VNEG TO MEET ADPA7006 VGG1 ABSOLUTE MAXIMUM RATINGS REQUIREMENT HMC980LP4E BIAS SEQUENCE CONSTANT DRAIN CURRENT BIASING vs. CONSTANT GATE VOLTAGE BIASING OUTLINE DIMENSIONS ORDERING GUIDE