Datasheet ADPA7002CHIP (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | GaAs, pHEMT, MMIC,1/2 W, 20 GHz to 44 GHz, Power Amplifier |
| 页数 / 页 | 23 / 3 — Data Sheet. ADPA7002CHIP. SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY … |
| 修订版 | C |
| 文件格式/大小 | PDF / 532 Kb |
| 文件语言 | 英语 |
Data Sheet. ADPA7002CHIP. SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE. Table 1. Parameter. Symbol Min. Typ. Max. Unit
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Data Sheet ADPA7002CHIP SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE
TA = 25°C, drain voltage (VDD) = 5 V, and quiescent drain current (IDQ) = 600 mA for nominal operation, unless otherwise noted.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 20 34 GHz GAIN 15 17 dB Gain Flatness ±0.5 dB Gain Variation over Temperature 0.012 dB/°C NOISE FIGURE 6 dB RETURN LOSS Input 20 dB Output 20 dB OUTPUT Output Power for 1 dB Compression P1dB 26 28.5 dBm Saturated Output Power PSAT 30 dBm Output Third-Order Intercept IP3 40 dBm Measurement taken at output power (POUT) per tone = 14 dBm SUPPLY Quiescent Drain Current IDQ 600 mA Adjust VGG1 between −1.5 V to 0 V to achieve the desired IDQ Drain Voltage VDD 4 5 V
34 GHz TO 44 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 600 mA for nominal operation, unless otherwise noted.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 34 44 GHz GAIN 12 15 dB Gain Flatness ±0.7 dB Gain Variation over Temperature 0.024 dB/°C NOISE FIGURE 5 dB RETURN LOSS Input 25 dB Output 16 dB OUTPUT Output Power for 1 dB Compression P1dB 25 28 dBm Saturated Output Power PSAT 28.5 dBm Output Third-Order Intercept IP3 40 dBm Measurement taken at POUT per tone = 14 dBm SUPPLY Quiescent Drain Current IDQ 600 mA Adjust VGG1 between −1.5 V to 0 V to achieve the desired IDQ Drain Voltage VDD 4 5 V Rev. C | Page 3 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS CONSTANT DRAIN CURRENT (IDD) OPERATION THEORY OF OPERATION ADPA7002CHIP ASSEMBLY AND CIRCUIT DIAGRAMS ALTERNATE ASSEMBLY DIAGRAM BIASING PROCEDURES BIASING THE ADPA7002CHIP WITH THE HMC980LP4E Application Circuit Setup Limiting VGATE to Meet ADPA7002CHIP VGGx AMR Requirement HMC980LP4E Bias Sequence Constant Drain Current Bias vs. Constant Gate Voltage Bias MOUNTING AND BONDING TECHNIQUES FOR MILLIMETER WAVE GAAS MMICS Handling Precautions Mounting Wire Bonding OUTLINE DIMENSIONS ORDERING GUIDE
TA = 25°C, drain voltage (VDD) = 5 V, and quiescent drain current (IDQ) = 600 mA for nominal operation, unless otherwise noted.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 20 34 GHz GAIN 15 17 dB Gain Flatness ±0.5 dB Gain Variation over Temperature 0.012 dB/°C NOISE FIGURE 6 dB RETURN LOSS Input 20 dB Output 20 dB OUTPUT Output Power for 1 dB Compression P1dB 26 28.5 dBm Saturated Output Power PSAT 30 dBm Output Third-Order Intercept IP3 40 dBm Measurement taken at output power (POUT) per tone = 14 dBm SUPPLY Quiescent Drain Current IDQ 600 mA Adjust VGG1 between −1.5 V to 0 V to achieve the desired IDQ Drain Voltage VDD 4 5 V
34 GHz TO 44 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 600 mA for nominal operation, unless otherwise noted.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 34 44 GHz GAIN 12 15 dB Gain Flatness ±0.7 dB Gain Variation over Temperature 0.024 dB/°C NOISE FIGURE 5 dB RETURN LOSS Input 25 dB Output 16 dB OUTPUT Output Power for 1 dB Compression P1dB 25 28 dBm Saturated Output Power PSAT 28.5 dBm Output Third-Order Intercept IP3 40 dBm Measurement taken at POUT per tone = 14 dBm SUPPLY Quiescent Drain Current IDQ 600 mA Adjust VGG1 between −1.5 V to 0 V to achieve the desired IDQ Drain Voltage VDD 4 5 V Rev. C | Page 3 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS CONSTANT DRAIN CURRENT (IDD) OPERATION THEORY OF OPERATION ADPA7002CHIP ASSEMBLY AND CIRCUIT DIAGRAMS ALTERNATE ASSEMBLY DIAGRAM BIASING PROCEDURES BIASING THE ADPA7002CHIP WITH THE HMC980LP4E Application Circuit Setup Limiting VGATE to Meet ADPA7002CHIP VGGx AMR Requirement HMC980LP4E Bias Sequence Constant Drain Current Bias vs. Constant Gate Voltage Bias MOUNTING AND BONDING TECHNIQUES FOR MILLIMETER WAVE GAAS MMICS Handling Precautions Mounting Wire Bonding OUTLINE DIMENSIONS ORDERING GUIDE