Datasheet HMC943APM5E (Analog Devices) - 5

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Data Sheet HMC943APM5E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ND C ND G V G1 V D1 V D3 V D5 NI V D7 G 32 31 30 29 28 27 26 25 GND 1 24 GND NIC 2 23 NIC GND 3 22 GND RF 4 HMC943APM5E IN 21 RFOUT GND 5 TOP VIEW 20 GND (Not to Scale) NIC 6 19 VDET NIC 7 18 VREF GND 8 17 GND 9 10 11 12 13 14 15 16 C ND ND G V G2 V D2 V D4 V D6 NI V D8 G NOTES
002
1. NIC = NOT INTERNALLY CONNECTED. 2. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND.
16864- Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1, 3, 5, 8, 9, GND Ground. These pins are exposed ground pads that must be connected to RF and dc ground. 16, 17, 20, 22, 24, 25, 32 2, 6, 7, 14, NIC Not Internally Connected. These pins are not connected internally. However, all data is measured with 23, 27 these pins connected to RF and dc ground externally. 4 RFIN RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface schematic. 10, 31 VG2, VG1 Gate Control for the Amplifier. Adjust VGx to achieve the recommended bias current. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required. See Figure 7 for the VGx interface schematic. VG1 and VG2 are internally connected. Therefore, external bias can be applied to either VG1 or VG2. 11, 12, 13, VD2, VD4, VD6, VD8, Drain Bias for the Amplifier. External bypass capacitors of 100 pF, 0.01 µF, and 4.7 µF are required on each 15, 26, 28, VD7, VD5, VD3, and pin. See Figure 5 for the VDx interface schematic. 29, 30 VD1 18 VREF Reference Diode Used for Temperature Compensation of VDET RF Output Power Measurements. Used in combination with VDET, this voltage provides temperature compensation to VDET RF output power measurements. See Figure 8 for the VREF interface schematic. 19 VDET Detector Diode Used for Measurement of the RF Output Power. Detection via this pin requires the application of a dc bias voltage through the external series resistor. Used in combination with VREF, the difference voltage, VREF − VDET, is a temperature compensated dc voltage proportional to the RF output power. See Figure 9 for the VDET interface schematic. 21 RFOUT RF Signal Output. This pad is dc-coupled and matched to 50 Ω over the operating frequency range. See Figure 6 for the RFOUT interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground. Rev. B | Page 5 of 18 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION POWER DETECTION EVALUATION BOARD EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE