Datasheet HMC1114PM5E (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | >10 W (42 dBm), 2.7 GHz to 3.8 GHz, GaN Power Amplifier |
| 页数 / 页 | 17 / 6 — HMC1114PM5E. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. ND … |
| 文件格式/大小 | PDF / 675 Kb |
| 文件语言 | 英语 |
HMC1114PM5E. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. ND C. C C
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HMC1114PM5E Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ND C C C ND G NI V DD1 NI NI V DD2 V DD2 G 32 31 30 29 28 27 26 25 GND 1 24 GND NIC 2 23 NIC NIC 3 HMC1114PM5E 22 NIC RFIN 4 21 RFOUT TOP VIEW RFIN 5 (Not to Scale) 20 RFOUT NIC 6 19 NIC NIC 7 18 NIC GND 8 17 GND 9 10 11 12 13 14 15 16 C C C C ND ND G NI NI NI NI V GG1 V GG2 G NOTES 1. NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY. HOWEVER, ALL DATA IS MEASURED WITH THESE PINS CONNECTED TO RF AND DC GROUND EXTERNALLY.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND.
16824- Figure 2. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1, 8, 9, 16, 17, 24, 25, 32 GND Ground. These pins must be connected to RF and dc ground. See Figure 3 for the GND interface schematic. 2, 3, 6, 7, 11, 12, 14, 15, NIC Not Internally Connected. These pins are not connected internally. However, all data is 18, 19, 22, 23, 28, 29, 31 measured with these pins connected to RF and dc ground externally. 4, 5 RFIN RF Input. These pins are ac-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface schematic. 10, 13 VGG1, VGG2 Gate Control Voltage Pins. External bypass capacitors of 1 µF and 10 µF are required. See Figure 5 for the VGG1 and VGG2 interface schematic. 20, 21 RFOUT RF Output. These pins are ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface schematic. 26, 27, 30 VDD1, VDD2 Drain Bias Pins for the Amplifier. External bypass capacitors of 1000 pF, 1 µF, and 10 µF are required. See Figure 7 for the VDD1 and VDD2 interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS GND
003
RFOUT
006 16824- 16824- Figure 3. GND Interface Figure 6. RFOUT Interface
VDD1, VDD2 RFIN
007 004 16824- 16824- Figure 4. RFIN Interface Figure 7. VDD1 and VDD2 Interface
VGG1, VGG2
005 16824- Figure 5. VGG1 and VGG2 Interface Rev. 0 | Page 6 of 17 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS TOTAL SUPPLY CURRENT BY VDD ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCE During Power-Up During Power-Down TYPICAL APPLICATION CIRCUIT EVALUATION PCB OUTLINE DIMENSIONS ORDERING GUIDE
HMC1114PM5E Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ND C C C ND G NI V DD1 NI NI V DD2 V DD2 G 32 31 30 29 28 27 26 25 GND 1 24 GND NIC 2 23 NIC NIC 3 HMC1114PM5E 22 NIC RFIN 4 21 RFOUT TOP VIEW RFIN 5 (Not to Scale) 20 RFOUT NIC 6 19 NIC NIC 7 18 NIC GND 8 17 GND 9 10 11 12 13 14 15 16 C C C C ND ND G NI NI NI NI V GG1 V GG2 G NOTES 1. NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY. HOWEVER, ALL DATA IS MEASURED WITH THESE PINS CONNECTED TO RF AND DC GROUND EXTERNALLY.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND.
16824- Figure 2. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1, 8, 9, 16, 17, 24, 25, 32 GND Ground. These pins must be connected to RF and dc ground. See Figure 3 for the GND interface schematic. 2, 3, 6, 7, 11, 12, 14, 15, NIC Not Internally Connected. These pins are not connected internally. However, all data is 18, 19, 22, 23, 28, 29, 31 measured with these pins connected to RF and dc ground externally. 4, 5 RFIN RF Input. These pins are ac-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface schematic. 10, 13 VGG1, VGG2 Gate Control Voltage Pins. External bypass capacitors of 1 µF and 10 µF are required. See Figure 5 for the VGG1 and VGG2 interface schematic. 20, 21 RFOUT RF Output. These pins are ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface schematic. 26, 27, 30 VDD1, VDD2 Drain Bias Pins for the Amplifier. External bypass capacitors of 1000 pF, 1 µF, and 10 µF are required. See Figure 7 for the VDD1 and VDD2 interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS GND
003
RFOUT
006 16824- 16824- Figure 3. GND Interface Figure 6. RFOUT Interface
VDD1, VDD2 RFIN
007 004 16824- 16824- Figure 4. RFIN Interface Figure 7. VDD1 and VDD2 Interface
VGG1, VGG2
005 16824- Figure 5. VGG1 and VGG2 Interface Rev. 0 | Page 6 of 17 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS TOTAL SUPPLY CURRENT BY VDD ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCE During Power-Up During Power-Down TYPICAL APPLICATION CIRCUIT EVALUATION PCB OUTLINE DIMENSIONS ORDERING GUIDE