Datasheet HMC1132PM5E (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 27 GHz to 32 GHz, GaAs, pHEMT, MMIC Power Amplifier |
| 页数 / 页 | 17 / 5 — Data Sheet. HMC1132PM5E. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GND … |
| 文件格式/大小 | PDF / 351 Kb |
| 文件语言 | 英语 |
Data Sheet. HMC1132PM5E. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GND 1. 24 GND. NIC 2. 23 NIC. NIC 3. 22 NIC. GND 4. 21 GND. TOP VIEW
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Data Sheet HMC1132PM5E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C C C C C ND GG ND G V NI NI NI NI NI G 32 31 30 29 28 27 26 25 GND 1 24 GND NIC 2 23 NIC NIC 3 22 NIC HMC1132PM5E GND 4 21 GND TOP VIEW RFIN 5 20 RFOUT (Not to Scale) GND 6 19 GND NIC 7 18 NIC GND 8 17 GND 9 10 11 12 13 14 15 16 C C 1 C 2 ND NI NI NC NI ND G DD DD V V G NOTES 1. NIC = NOT INTERNALLY CONNECTED.
002
2. THE EXPOSED PAD. EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND.
17225- Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 6, 8, 9, 16, 17, 19, GND Ground. These pins and the exposed pad must be connected to RF and dc ground. 21, 24, 25, 32 2, 3, 7, 10, 11, 13, 14, NIC Not Internally Connected. These pins are not connected internally. However, all data was measured 18, 22, 23, 26 to 30 with these pins connected to RF and dc ground externally. 5 RFIN RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface schematic. 12, 15 VDD1, VDD2 Drain Bias Voltage. External 100 pF, 10 nF, and 4.7 μF bypass capacitors are required. See Figure 5 for the VDD1 and VDD2 interface schematic. 20 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface schematic. 31 VGG Gate Control for Amplifier. Adjust VGG to achieve the recommended bias current. External 100 pF, 10 nF, and 4.7 μF bypass capacitors are required. See Figure 7 for the VGG interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS GND
003 006 17225-
RFOUT
17225- Figure 3. GND Interface Figure 6. RFOUT Interface
RFIN
007 004
VGG
17225- 17225- Figure 7. VGG Interface Figure 4. RFIN Interface
VDD1,VDD2
005 17225- Figure 5. VDD1 and VDD2 Interface Rev. 0 | Page 5 of 17 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Application Circuit Evaluation Board Bill of Materials Evaluation Board Schematic Outline Dimensions Ordering Guide
Data Sheet HMC1132PM5E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C C C C C ND GG ND G V NI NI NI NI NI G 32 31 30 29 28 27 26 25 GND 1 24 GND NIC 2 23 NIC NIC 3 22 NIC HMC1132PM5E GND 4 21 GND TOP VIEW RFIN 5 20 RFOUT (Not to Scale) GND 6 19 GND NIC 7 18 NIC GND 8 17 GND 9 10 11 12 13 14 15 16 C C 1 C 2 ND NI NI NC NI ND G DD DD V V G NOTES 1. NIC = NOT INTERNALLY CONNECTED.
002
2. THE EXPOSED PAD. EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND.
17225- Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 6, 8, 9, 16, 17, 19, GND Ground. These pins and the exposed pad must be connected to RF and dc ground. 21, 24, 25, 32 2, 3, 7, 10, 11, 13, 14, NIC Not Internally Connected. These pins are not connected internally. However, all data was measured 18, 22, 23, 26 to 30 with these pins connected to RF and dc ground externally. 5 RFIN RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface schematic. 12, 15 VDD1, VDD2 Drain Bias Voltage. External 100 pF, 10 nF, and 4.7 μF bypass capacitors are required. See Figure 5 for the VDD1 and VDD2 interface schematic. 20 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface schematic. 31 VGG Gate Control for Amplifier. Adjust VGG to achieve the recommended bias current. External 100 pF, 10 nF, and 4.7 μF bypass capacitors are required. See Figure 7 for the VGG interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS GND
003 006 17225-
RFOUT
17225- Figure 3. GND Interface Figure 6. RFOUT Interface
RFIN
007 004
VGG
17225- 17225- Figure 7. VGG Interface Figure 4. RFIN Interface
VDD1,VDD2
005 17225- Figure 5. VDD1 and VDD2 Interface Rev. 0 | Page 5 of 17 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Application Circuit Evaluation Board Bill of Materials Evaluation Board Schematic Outline Dimensions Ordering Guide