Datasheet HMC1099 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | >10 W, GaN Power Amplifier, 0.01 GHz to 1.1 GHz |
| 页数 / 页 | 16 / 6 — HMC1099. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GND 1. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 395 Kb |
| 文件语言 | 英语 |
HMC1099. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GND 1. 24 GND. NIC 2. 23 NIC. NIC 3. 22 NIC. RFIN/V. 21 RFOUT/VDD. TOP VIEW
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HMC1099 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ND IC IC IC IC IC IC ND G N N N N N N G 2 1 0 9 8 7 6 5 3 3 3 2 2 2 2 2 GND 1 24 GND NIC 2 23 NIC NIC 3 22 NIC HMC1099 RFIN/V 4 GG 21 RFOUT/VDD TOP VIEW RFIN/V 5 GG 20 RFOUT/VDD (Not to Scale) NIC 6 19 NIC NIC 7 18 NIC GND 8 17 GND 9 0 1 2 1 3 4 5 6 1 1 1 1 1 1 D D N IC IC IC IC IC IC N N N N N N N G G NOTES 1. EXPOSED PAD. EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND.
2 0
2. NO INTERNAL CONNECTION. THESE PINS
-0 5
ARE NOT CONNECTED INTERNALLY.
52 3 1 Figure 2. Pin Configuration
Table 6. Pad Function Descriptions Pin No. Mnemonic Description
1, 8, 9, 16, 17, 24, 25, 32 GND Ground. These pins must be connected to RF/dc ground. See Figure 3 for the GND interface schematic. 2, 3, 6, 7, 10 to 15, 18, NIC No Internal Connection. These pins are not connected internally. However, all data was measured 19, 22, 23, 26 to 31 with these pins connected to RF/dc ground externally. 4, 5 RFIN/VGG RF Input (RFIN)/Gate Bias Control Voltage (VGG). This pin is a multifunction pin. The RFIN/VGG pin is dc-coupled with internal prematching and requires external matching to 50 Ω, as shown in Figure 38. See Figure 4 for the RFIN/VGG interface schematic. 20, 21 RFOUT/VDD RF Output (RFOUT)/Drain Bias Voltage (VDD). This is a multifunction pin. The RFOUT/VDD pin is dc-coupled and requires external matching to 50 Ω, as shown in Figure 38. See Figure 4 for the RFOUT/VDD interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS RFOUT/VDD GND
003
RFIN/VGG
004 13525- 13525- Figure 3. GND Interface Figure 4. RFIN/VGG and RFOUT/VDD Interface Rev. A | Page 6 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS TOTAL SUPPLY CURRENT BY VDD ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT EVALUATION PCB BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE
HMC1099 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ND IC IC IC IC IC IC ND G N N N N N N G 2 1 0 9 8 7 6 5 3 3 3 2 2 2 2 2 GND 1 24 GND NIC 2 23 NIC NIC 3 22 NIC HMC1099 RFIN/V 4 GG 21 RFOUT/VDD TOP VIEW RFIN/V 5 GG 20 RFOUT/VDD (Not to Scale) NIC 6 19 NIC NIC 7 18 NIC GND 8 17 GND 9 0 1 2 1 3 4 5 6 1 1 1 1 1 1 D D N IC IC IC IC IC IC N N N N N N N G G NOTES 1. EXPOSED PAD. EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND.
2 0
2. NO INTERNAL CONNECTION. THESE PINS
-0 5
ARE NOT CONNECTED INTERNALLY.
52 3 1 Figure 2. Pin Configuration
Table 6. Pad Function Descriptions Pin No. Mnemonic Description
1, 8, 9, 16, 17, 24, 25, 32 GND Ground. These pins must be connected to RF/dc ground. See Figure 3 for the GND interface schematic. 2, 3, 6, 7, 10 to 15, 18, NIC No Internal Connection. These pins are not connected internally. However, all data was measured 19, 22, 23, 26 to 31 with these pins connected to RF/dc ground externally. 4, 5 RFIN/VGG RF Input (RFIN)/Gate Bias Control Voltage (VGG). This pin is a multifunction pin. The RFIN/VGG pin is dc-coupled with internal prematching and requires external matching to 50 Ω, as shown in Figure 38. See Figure 4 for the RFIN/VGG interface schematic. 20, 21 RFOUT/VDD RF Output (RFOUT)/Drain Bias Voltage (VDD). This is a multifunction pin. The RFOUT/VDD pin is dc-coupled and requires external matching to 50 Ω, as shown in Figure 38. See Figure 4 for the RFOUT/VDD interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS RFOUT/VDD GND
003
RFIN/VGG
004 13525- 13525- Figure 3. GND Interface Figure 4. RFIN/VGG and RFOUT/VDD Interface Rev. A | Page 6 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS TOTAL SUPPLY CURRENT BY VDD ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT EVALUATION PCB BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE