Datasheet ADRF5515 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | Dual-Channel, 3.3 GHz to 4.0 GHz, 20 W Receiver Front End |
| 页数 / 页 | 15 / 1 — Dual-Channel, 3.3 GHz to 4.0 GHz,. 20 W Receiver Front End. Data Sheet. … |
| 文件格式/大小 | PDF / 413 Kb |
| 文件语言 | 英语 |
Dual-Channel, 3.3 GHz to 4.0 GHz,. 20 W Receiver Front End. Data Sheet. ADRF5515. FEATURES. FUNCTIONAL BLOCK DIAGRAM
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Dual-Channel, 3.3 GHz to 4.0 GHz, 20 W Receiver Front End Data Sheet ADRF5515 FEATURES FUNCTIONAL BLOCK DIAGRAM Integrated dual-channel RF front end ADRF5515 2-stage LNA and high power silicon SPDT switch On-chip bias and matching -CHA CHA CHA Single-supply operation RM C C C ND E ND ND DD1- C DD2- Gain G T NI NI G G V NI NI V High gain mode: 33 dB typical at 3.6 GHz 40 39 38 37 36 35 34 33 32 31 Low gain mode: 16 dB typical at 3.6 GHz GND 1 30 GND Low noise figure GND 2 29 RXOUT-CHA ANT-CHA 3 28 GND High gain mode: 1.0 dB typical at 3.6 GHz GND 4 27 BP-CHA SWCTRL-CHAB 5 26 PD-CHAB Low gain mode: 1.0 dB typical at 3.6 GHz SWVDD-CHAB 6 25 NIC GND 7 24 BP-CHB High isolation ANT-CHB 8 23 GND GND 9 22 RXOUT-CHB RXOUT-CHA and RXOUT-CHB: 45 dB typical GND 10 21 GND TERM-CHA and TERM-CHB: 60 dB typical 11 12 13 14 15 16 17 18 19 20 Low insertion loss: 0.45 dB typical at 3.6 GHz C C C C ND NI ND ND NI NI NI High power handling at T G G G CHB CHB CASE = 105°C -CHB
001
Full lifetime RM E DD1- DD2- T V V
20051-
LTE average power (9 dB PAR): 43 dBm
Figure 1.
High OIP3 (high gain mode): 32 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 86 mA typical at 5 V Low gain mode: 36 mA typical at 5 V Power-down mode: 12 mA typical at 5 V Positive logic control 6 mm × 6 mm, 40-lead LFCSP Pin compatible with the ADRF5545A, 10 W version APPLICATIONS Wireless infrastructure TDD massive multiple input and multiple output and active antenna systems TDD-based communication systems GENERAL DESCRIPTION
In transmit operation, when RF inputs are connected to a The ADRF5515 is a dual-channel, integrated RF, front-end, termination pin (TERM-CHA or TERM-CHB), the switch multichip module designed for time division duplexing (TDD) applications. The device operates from 3.3 GHz to 4.0 GHz. provides low insertion loss of 0.45 dB and handles long-term The ADRF5515 is configured in dual channels with a cascading, evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 43 dBm for ful lifetime operation. two-stage, LNA and a high power silicon SPDT switch. In high gain mode, the cascaded two-stage LNA and switch The ADRF5515 is pin-compatible with the ADRF5545A, 10 W offer a low noise figure of 1.0 dB and a high gain of 33 dB at version, which operates from 2.4 GHz to 4.2 GHz. 3.6 GHz with an output third-order intercept point (OIP3) of The ADRF5515 does not require any matching components at 32 dBm (typical). In low gain mode, one stage of the two-stage the RF ports that are internal y matched to 50 Ω. The ANT and LNA is in bypass, providing 16 dB of gain at a lower current of TERM ports are also internally ac-coupled. Therefore, only 36 mA. In power-down mode, the LNAs are turned off and the receiver ports require external dc blocking capacitors. device draws 12 mA. The device comes in an RoHS compliant, compact, 6 mm × 6 mm, 40-lead LFCSP.
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings for ADRF5515 ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVE OPERATION, HIGH GAIN MODE RECEIVE OPERATION, LOW GAIN MODE TRANSMIT OPERATION THEORY OF OPERATION SIGNAL PATH SELECT Transmit Operation Receive Operation BIASING SEQUENCE APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
Dual-Channel, 3.3 GHz to 4.0 GHz, 20 W Receiver Front End Data Sheet ADRF5515 FEATURES FUNCTIONAL BLOCK DIAGRAM Integrated dual-channel RF front end ADRF5515 2-stage LNA and high power silicon SPDT switch On-chip bias and matching -CHA CHA CHA Single-supply operation RM C C C ND E ND ND DD1- C DD2- Gain G T NI NI G G V NI NI V High gain mode: 33 dB typical at 3.6 GHz 40 39 38 37 36 35 34 33 32 31 Low gain mode: 16 dB typical at 3.6 GHz GND 1 30 GND Low noise figure GND 2 29 RXOUT-CHA ANT-CHA 3 28 GND High gain mode: 1.0 dB typical at 3.6 GHz GND 4 27 BP-CHA SWCTRL-CHAB 5 26 PD-CHAB Low gain mode: 1.0 dB typical at 3.6 GHz SWVDD-CHAB 6 25 NIC GND 7 24 BP-CHB High isolation ANT-CHB 8 23 GND GND 9 22 RXOUT-CHB RXOUT-CHA and RXOUT-CHB: 45 dB typical GND 10 21 GND TERM-CHA and TERM-CHB: 60 dB typical 11 12 13 14 15 16 17 18 19 20 Low insertion loss: 0.45 dB typical at 3.6 GHz C C C C ND NI ND ND NI NI NI High power handling at T G G G CHB CHB CASE = 105°C -CHB
001
Full lifetime RM E DD1- DD2- T V V
20051-
LTE average power (9 dB PAR): 43 dBm
Figure 1.
High OIP3 (high gain mode): 32 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 86 mA typical at 5 V Low gain mode: 36 mA typical at 5 V Power-down mode: 12 mA typical at 5 V Positive logic control 6 mm × 6 mm, 40-lead LFCSP Pin compatible with the ADRF5545A, 10 W version APPLICATIONS Wireless infrastructure TDD massive multiple input and multiple output and active antenna systems TDD-based communication systems GENERAL DESCRIPTION
In transmit operation, when RF inputs are connected to a The ADRF5515 is a dual-channel, integrated RF, front-end, termination pin (TERM-CHA or TERM-CHB), the switch multichip module designed for time division duplexing (TDD) applications. The device operates from 3.3 GHz to 4.0 GHz. provides low insertion loss of 0.45 dB and handles long-term The ADRF5515 is configured in dual channels with a cascading, evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 43 dBm for ful lifetime operation. two-stage, LNA and a high power silicon SPDT switch. In high gain mode, the cascaded two-stage LNA and switch The ADRF5515 is pin-compatible with the ADRF5545A, 10 W offer a low noise figure of 1.0 dB and a high gain of 33 dB at version, which operates from 2.4 GHz to 4.2 GHz. 3.6 GHz with an output third-order intercept point (OIP3) of The ADRF5515 does not require any matching components at 32 dBm (typical). In low gain mode, one stage of the two-stage the RF ports that are internal y matched to 50 Ω. The ANT and LNA is in bypass, providing 16 dB of gain at a lower current of TERM ports are also internally ac-coupled. Therefore, only 36 mA. In power-down mode, the LNAs are turned off and the receiver ports require external dc blocking capacitors. device draws 12 mA. The device comes in an RoHS compliant, compact, 6 mm × 6 mm, 40-lead LFCSP.
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings for ADRF5515 ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVE OPERATION, HIGH GAIN MODE RECEIVE OPERATION, LOW GAIN MODE TRANSMIT OPERATION THEORY OF OPERATION SIGNAL PATH SELECT Transmit Operation Receive Operation BIASING SEQUENCE APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE