Datasheet AD8317 (Analog Devices) - 10

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AD8317 Data Sheet THEORY OF OPERATION
The AD8317 is a 6-stage demodulating logarithmic amplifier, characteristic to partially compensate for errors due to internal specifically designed for use in RF measurement and power noise. The common pin, COMM, provides a quality low control applications at frequencies up to 10 GHz. A block impedance connection to the printed circuit board (PCB) diagram is shown in Figure 21. Sharing much of its design ground. The package paddle, which is internally connected to the with the AD8318 logarithmic detector/controller, the AD8317 COMM pin, must also be grounded to the PCB to reduce thermal maintains tight intercept variability vs. temperature over a 50 dB impedance from the die to the PCB. range. Additional enhancements over the AD8318, such as a The logarithmic function is approximated in a piecewise reduced RF burst response time of 6 ns to 10 ns, 22 mA supply fashion by six cascaded gain stages. (For a more comprehensive current, and board space requirements of only 2 mm × 3 mm, explanation of the logarithm approximation, see the AD8307 add to the low cost and high performance benefits of the AD8317. data sheet.) The cells have a nominal voltage gain of 9 dB each
VPOS TADJ
and a 3 dB bandwidth of 10.5 GHz. Using precision biasing, the gain is stabilized over temperature and supply variations. The
GAIN BIAS SLOPE V I VSET
overall dc gain is high, due to the cascaded nature of the gain stages. An offset compensation loop is included to correct for
I V VOUT
offsets within the cascaded cells. At the output of each of the
DET DET DET DET
gain stages, a square-law detector cell is used to rectify the signal.
CLPF INHI
The RF signal voltages are converted to a fluctuating differential
INLO
current having an average value that increases with signal level. 21 0 Along with the six gain stages and detector cells, an additional 1-
COMM
54 05 detector is included at the input of the AD8317, providing a Figure 21. Block Diagram 50 dB dynamic range in total. After the detector currents are summed and filtered, the following function is formed at the A fully differential design, using a proprietary, high speed SiGe summing node: process, extends high frequency performance. Input INHI receives the signal with a low frequency impedance of nominally 500 Ω in ID × log10(VIN/VINTERCEPT) (1) parallel with 0.7 pF. The maximum input with ±1 dB log- where: conformance error is typically 0 dBm (referenced to 50 Ω). The ID is the internally set detector current. noise spectral density referred to the input is 1.15 nV/Hz, VIN is the input signal voltage. which is equivalent to a voltage of 118 μV rms in a 10.5 GHz VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT, bandwidth or a noise power of −66 dBm (referenced to 50 Ω). the output voltage would be 0 V, if it were capable of going to 0 V). This noise spectral density sets the lower limit of the dynamic range. However, the low end accuracy of the AD8317 is enhanced by specially shaping the demodulating transfer Rev. D | Page 10 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD8317 BASIC CONNECTIONS INPUT SIGNAL COUPLING OUTPUT INTERFACE SETPOINT INTERFACE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE MEASUREMENT MODE SETTING THE OUTPUT SLOPE IN MEASUREMENT MODE CONTROLLER MODE OUTPUT FILTERING OPERATION BEYOND 8 GHz EVALUATION BOARD DIE INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE