Datasheet AD8315 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 50 dB GSM PA Controller |
| 页数 / 页 | 22 / 3 — Data Sheet. AD8315. SPECIFICATIONS. Table 1. Parameter Test. … |
| 修订版 | D |
| 文件格式/大小 | PDF / 450 Kb |
| 文件语言 | 英语 |
Data Sheet. AD8315. SPECIFICATIONS. Table 1. Parameter Test. Conditions/Comments. Min. Typ. Max. Unit
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Data Sheet AD8315 SPECIFICATIONS
VS = 2.7 V, T = 25°C, 52.3 Ω termination on RFIN, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL FUNCTION Frequency Range1 To meet all specifications 0.1 2.5 GHz Input Voltage Range ±1 dB log conformance, 0.1 GHz −57 −11 dBV Equivalent dBm Range −44 +2 dBm Logarithmic Slope2 0.1 GH 21.5 24 25.5 mV/dB Logarithmic Intercept2 0.1 GHz −79 −70 −64 dBV Equivalent dBm Level −66 −57 −51 dBm RF INPUT INTERFACE Pin RFIN Input Resistance3 0.1 GHz 2.8 kΩ Input Capacitance3 0.1 GHz 0.9 pF OUTPUT Pin VAPC Minimum Output Voltage VSET ≤ 200 mV, ENBL high 0.25 0.27 0.3 V ENBL low 0.02 V Maximum Output Voltage RL ≥ 800 Ω 2.45 2.6 V vs. Temperature4 85°C, VPOS = 3 V, IOUT = 6 mA 2.54 V General Limit 2.7 V ≤ VPOS ≤ 5.5 V, RL = ∞ VPOS − 0.1 V Output Current Drive Source/Sink 5/200 mA/μA Output Buffer Noise 25 nV√Hz Output Noise RF input = 2 GHz, 0 dBm, fNOISE = 100 kHz, CFLT = 220 pF 130 nV/√Hz Small Signal Bandwidth 0.2 V to 2.6 V swing 30 MHz Slew Rate 10% to 90%, 1.2 V step (VSET), open loop5 13 V/μs Response Time FLTR = open, see Figure 27 150 ns SETPOINT INTERFACE Pin VSET Nominal Input Range Corresponding to central 50 dB 0.25 1.4 V Logarithmic Scale Factor 43.5 dB/V Input Resistance 100 kΩ Slew Rate 16 V/μs ENABLE INTERFACE Pin ENBL Logic Level to Enable Power 1.8 VPOS V Input Current when Enable 20 μA High Logic Level to Disable Power 0.8 V Enable Time Time from ENBL high to VAPC within 1% of final value, 4 5 μs VSET ≤ 200 mV, refer to Figure 24 Disable Time Time from ENBL low to VAPC within 1% of final value, 8 9 μs VSET ≤ 200 mV, refer to Figure 24 Power-On/Enable Time Time from VPOS/ENBL high to VAPC within 1% of final value, 2 3 μs VSET ≤ 200 mV, refer to Figure 29 Time from VPOS/ENBL low to VAPC within 1% of final value, 100 200 ns VSET ≤ 200 mV, refer to Figure 29 Rev. D | Page 3 of 22 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC THEORY CONTROLLER-MODE LOG AMPS CONTROL LOOP DYNAMICS Example PRACTICAL LOOP A NOTE ABOUT POWER EQUIVALENCY BASIC CONNECTIONS RANGE ON VSET AND RFIN TRANSIENT RESPONSE MOBILE HANDSET POWER CONTROL EXAMPLE ENABLE AND POWER-ON INPUT COUPLING OPTIONS USING THE CHIP SCALE PACKAGE EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD8315 SPECIFICATIONS
VS = 2.7 V, T = 25°C, 52.3 Ω termination on RFIN, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL FUNCTION Frequency Range1 To meet all specifications 0.1 2.5 GHz Input Voltage Range ±1 dB log conformance, 0.1 GHz −57 −11 dBV Equivalent dBm Range −44 +2 dBm Logarithmic Slope2 0.1 GH 21.5 24 25.5 mV/dB Logarithmic Intercept2 0.1 GHz −79 −70 −64 dBV Equivalent dBm Level −66 −57 −51 dBm RF INPUT INTERFACE Pin RFIN Input Resistance3 0.1 GHz 2.8 kΩ Input Capacitance3 0.1 GHz 0.9 pF OUTPUT Pin VAPC Minimum Output Voltage VSET ≤ 200 mV, ENBL high 0.25 0.27 0.3 V ENBL low 0.02 V Maximum Output Voltage RL ≥ 800 Ω 2.45 2.6 V vs. Temperature4 85°C, VPOS = 3 V, IOUT = 6 mA 2.54 V General Limit 2.7 V ≤ VPOS ≤ 5.5 V, RL = ∞ VPOS − 0.1 V Output Current Drive Source/Sink 5/200 mA/μA Output Buffer Noise 25 nV√Hz Output Noise RF input = 2 GHz, 0 dBm, fNOISE = 100 kHz, CFLT = 220 pF 130 nV/√Hz Small Signal Bandwidth 0.2 V to 2.6 V swing 30 MHz Slew Rate 10% to 90%, 1.2 V step (VSET), open loop5 13 V/μs Response Time FLTR = open, see Figure 27 150 ns SETPOINT INTERFACE Pin VSET Nominal Input Range Corresponding to central 50 dB 0.25 1.4 V Logarithmic Scale Factor 43.5 dB/V Input Resistance 100 kΩ Slew Rate 16 V/μs ENABLE INTERFACE Pin ENBL Logic Level to Enable Power 1.8 VPOS V Input Current when Enable 20 μA High Logic Level to Disable Power 0.8 V Enable Time Time from ENBL high to VAPC within 1% of final value, 4 5 μs VSET ≤ 200 mV, refer to Figure 24 Disable Time Time from ENBL low to VAPC within 1% of final value, 8 9 μs VSET ≤ 200 mV, refer to Figure 24 Power-On/Enable Time Time from VPOS/ENBL high to VAPC within 1% of final value, 2 3 μs VSET ≤ 200 mV, refer to Figure 29 Time from VPOS/ENBL low to VAPC within 1% of final value, 100 200 ns VSET ≤ 200 mV, refer to Figure 29 Rev. D | Page 3 of 22 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC THEORY CONTROLLER-MODE LOG AMPS CONTROL LOOP DYNAMICS Example PRACTICAL LOOP A NOTE ABOUT POWER EQUIVALENCY BASIC CONNECTIONS RANGE ON VSET AND RFIN TRANSIENT RESPONSE MOBILE HANDSET POWER CONTROL EXAMPLE ENABLE AND POWER-ON INPUT COUPLING OPTIONS USING THE CHIP SCALE PACKAGE EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE