Datasheet ADA4320-1 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Low Distortion, DOCSIS 3.0, Upstream CATV Line Driver |
| 页数 / 页 | 16 / 10 — –24. –22. SINGLE QPSK CHANNEL. 4× QAM64 CHANNELS (UNCORRELATED). –28 GAIN … |
| 修订版 | A |
| 文件格式/大小 | PDF / 365 Kb |
| 文件语言 | 英语 |
–24. –22. SINGLE QPSK CHANNEL. 4× QAM64 CHANNELS (UNCORRELATED). –28 GAIN CODE 42 (14dB). GAIN CODE 42 (14dB). Bc)
该数据表的模型线
文件文字版本
ADA4320-1
–24 –22 SINGLE QPSK CHANNEL 4× QAM64 CHANNELS (UNCORRELATED) –28 GAIN CODE 42 (14dB) GAIN CODE 42 (14dB) Bc) CHANNEL WIDTH = 6.4MHz Bc) CHANNEL WIDTH = 1.6MHz d –28 d DRIVEN CHANNEL CENTER = 77.8MHz, 79.4MHz, ( –32 DRIVEN CHANNEL CENTER = 42 MHz ( 81.0MHz, 82.6MHz IO ADJACENT CHANNEL WIDTH = 6.4 MHz IO ADJACENT CHANNEL WIDTH = 1.6MHz T –36 ADJACENT CHANNEL CENTER = 48.4 MHz T ADJACENT CHANNEL CENTER = 84.2MHz A –34 A R CURRENT LEVEL 0 –40 CURRENT LEVEL 0 R R R CURRENT LEVEL 1 E CURRENT LEVEL 1 E –40 CURRENT LEVEL 2 W –44 CURRENT LEVEL 2 W O CURRENT LEVEL 3 O CURRENT LEVEL 3 P –48 P L –46 L –52 NNE NNE –52 –56 CHA CHA T T N –60 N –58 –64 JACE JACE D –64 D A –68 A –72 –70
8 9
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
-01
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-01
INPUT LEVEL (dBmV)
707
INPUT LEVEL (dBmV/CHANNEL)
707 08 08 Figure 17. ACPR vs. Input Level for a Single QPSK Channel Figure 20. ACPR vs. Input Level for 4× QAM64 Channels
–10 –10 SINGLE QPSK CHANNEL 4× QAM64 CHANNELS (UNCORRELATED) GAIN CODE 60 (MAXIMUM) GAIN CODE 60 (MAXIMUM) Bc) CHANNEL WIDTH = 6.4MHz Bc) CHANNEL WIDTH = 1.6MHz d –20 DRIVEN CHANNEL CENTER = 42MHz d –20 DRIVEN CHANNEL CENTER = 77.8MHz, 79.4MHz, ( ADJACENT CHANNEL WIDTH = 6.4MHz ( 81.0MHz, 82.6MHz IO ADJACENT CHANNEL CENTER = 48.4MHz IO ADJACENT CHANNEL WIDTH = 1.6MHz T T ADJACENT CHANNEL CENTER = 84.2MHz A CURRENT LEVEL 0 –30 A –30 R CURRENT LEVEL 1 R CURRENT LEVEL 0 R CURRENT LEVEL 2 R E CURRENT LEVEL 1 CURRENT LEVEL 3 E W CURRENT LEVEL 2 –40 W O –40 O CURRENT LEVEL 3 P P L L –50 –50 NNE NNE CHA –60 CHA T –60 T N N JACE –70 JACE –70 D D A A –80 –80
0 1
59 60 61 62 63 64 65 66 67 68 69 70 71
-02
44 46 48 50 52 54 56 58 60 62
-02
OUTPUT LEVEL (dBmV)
707
OUTPUT LEVEL (dBmV/CHANNEL)
707 08 08 Figure 18. ACPR vs. Output Level for a Single QPSK Channel Figure 21. ACPR vs. Output Level for 4x QAM64 Channels
8 120 4× QAM64 CHANNELS (UNCORRELATED) TXEN = 1 OUTPUT LEVEL = 53dBmV/CHANNEL CHANNEL WIDTH = 1.6MHz TXEN = 0 6 CHANNEL CENTERS = 39.6MHz, 41.2MHz, 42.8MHz, 44.4MHz) -p) 100 DOCSIS 3.0 LIMIT (FOR 29dBmV INPUT) p V ) 4 TXEN m V ( ( E E D 80 2 U UD IT IT L L P P 0 M 60 A AM H C UT –2 P 40 UT GLIT O –4 T U P PEAK OUTPUT T 20 –6 ENVELOPE OU –8 0 –2 0 2 4 6 8 10 12 14 16 18
-022
0 6 12 18 24 30 36 42 48 54 60
-023 07
TIME (µs)
07
GAIN CODE
087 087 Figure 19. Transmit Enable/Disable Response Figure 22. Output Glitch Amplitude vs. Gain Code Rev. A | Page 10 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE
–24 –22 SINGLE QPSK CHANNEL 4× QAM64 CHANNELS (UNCORRELATED) –28 GAIN CODE 42 (14dB) GAIN CODE 42 (14dB) Bc) CHANNEL WIDTH = 6.4MHz Bc) CHANNEL WIDTH = 1.6MHz d –28 d DRIVEN CHANNEL CENTER = 77.8MHz, 79.4MHz, ( –32 DRIVEN CHANNEL CENTER = 42 MHz ( 81.0MHz, 82.6MHz IO ADJACENT CHANNEL WIDTH = 6.4 MHz IO ADJACENT CHANNEL WIDTH = 1.6MHz T –36 ADJACENT CHANNEL CENTER = 48.4 MHz T ADJACENT CHANNEL CENTER = 84.2MHz A –34 A R CURRENT LEVEL 0 –40 CURRENT LEVEL 0 R R R CURRENT LEVEL 1 E CURRENT LEVEL 1 E –40 CURRENT LEVEL 2 W –44 CURRENT LEVEL 2 W O CURRENT LEVEL 3 O CURRENT LEVEL 3 P –48 P L –46 L –52 NNE NNE –52 –56 CHA CHA T T N –60 N –58 –64 JACE JACE D –64 D A –68 A –72 –70
8 9
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
-01
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-01
INPUT LEVEL (dBmV)
707
INPUT LEVEL (dBmV/CHANNEL)
707 08 08 Figure 17. ACPR vs. Input Level for a Single QPSK Channel Figure 20. ACPR vs. Input Level for 4× QAM64 Channels
–10 –10 SINGLE QPSK CHANNEL 4× QAM64 CHANNELS (UNCORRELATED) GAIN CODE 60 (MAXIMUM) GAIN CODE 60 (MAXIMUM) Bc) CHANNEL WIDTH = 6.4MHz Bc) CHANNEL WIDTH = 1.6MHz d –20 DRIVEN CHANNEL CENTER = 42MHz d –20 DRIVEN CHANNEL CENTER = 77.8MHz, 79.4MHz, ( ADJACENT CHANNEL WIDTH = 6.4MHz ( 81.0MHz, 82.6MHz IO ADJACENT CHANNEL CENTER = 48.4MHz IO ADJACENT CHANNEL WIDTH = 1.6MHz T T ADJACENT CHANNEL CENTER = 84.2MHz A CURRENT LEVEL 0 –30 A –30 R CURRENT LEVEL 1 R CURRENT LEVEL 0 R CURRENT LEVEL 2 R E CURRENT LEVEL 1 CURRENT LEVEL 3 E W CURRENT LEVEL 2 –40 W O –40 O CURRENT LEVEL 3 P P L L –50 –50 NNE NNE CHA –60 CHA T –60 T N N JACE –70 JACE –70 D D A A –80 –80
0 1
59 60 61 62 63 64 65 66 67 68 69 70 71
-02
44 46 48 50 52 54 56 58 60 62
-02
OUTPUT LEVEL (dBmV)
707
OUTPUT LEVEL (dBmV/CHANNEL)
707 08 08 Figure 18. ACPR vs. Output Level for a Single QPSK Channel Figure 21. ACPR vs. Output Level for 4x QAM64 Channels
8 120 4× QAM64 CHANNELS (UNCORRELATED) TXEN = 1 OUTPUT LEVEL = 53dBmV/CHANNEL CHANNEL WIDTH = 1.6MHz TXEN = 0 6 CHANNEL CENTERS = 39.6MHz, 41.2MHz, 42.8MHz, 44.4MHz) -p) 100 DOCSIS 3.0 LIMIT (FOR 29dBmV INPUT) p V ) 4 TXEN m V ( ( E E D 80 2 U UD IT IT L L P P 0 M 60 A AM H C UT –2 P 40 UT GLIT O –4 T U P PEAK OUTPUT T 20 –6 ENVELOPE OU –8 0 –2 0 2 4 6 8 10 12 14 16 18
-022
0 6 12 18 24 30 36 42 48 54 60
-023 07
TIME (µs)
07
GAIN CODE
087 087 Figure 19. Transmit Enable/Disable Response Figure 22. Output Glitch Amplitude vs. Gain Code Rev. A | Page 10 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE