Datasheet AD8325 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 5 V CATV Line Driver Fine Step Output Power Control |
| 页数 / 页 | 16 / 3 — AD8325. LOGIC INPUTS (TTL/CMOS-Compatible Logic) (DATEN, CLK, SDATA, … |
| 修订版 | A |
| 文件格式/大小 | PDF / 749 Kb |
| 文件语言 | 英语 |
AD8325. LOGIC INPUTS (TTL/CMOS-Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V: Full Temperature Range)
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AD8325 LOGIC INPUTS (TTL/CMOS-Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V: Full Temperature Range) Parameter Min Typ Max Unit
Logic “1” Voltage 2.1 5.0 V Logic “0” Voltage 0 0.8 V Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN 0 20 nA Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN –600 –100 nA Logic “1” Current (VINH = 5 V) TXEN 50 190 mA Logic “0” Current (VINL = 0 V) TXEN –250 –30 mA Logic “1” Current (VINH = 5 V) SLEEP 50 190 mA Logic “0” Current (VINL = 0 V) SLEEP –250 –30 mA
TIMING REQUIREMENTS (Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.) Parameter Min Typ Max Unit
Clock Pulsewidth (TWH) 16.0 ns Clock Period (TC) 32.0 ns Setup Time SDATA vs. Clock (TDS) 5.0 ns Setup Time DATEN vs. Clock (TES) 15.0 ns Hold Time SDATA vs. Clock (TDH) 5.0 ns Hold Time DATEN vs. Clock (TEH) 3.0 ns Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF) 10 ns
TDS VALID DATA WORD G1 SDATA VALID DATA WORD G2 MSB. .LSB TC TWH CLK TES TEH 8 CLOCK DATEN CYCLES GAIN TRANSFER (G1) GAIN TRANSFER (G2) TOFF TXEN TGS TON ANALOG OUTPUT SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Timing
VALID DATA BIT SDATA MSB MSB-1 MSB-2 TDS TDH CLK
Figure 3. SDATA Timing REV. A –3– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS LOGIC INPUTS TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics APPLICATIONS General Application Operational Description SPI Programming and Gain Adjustment Input Bias, Impedance, and Termination Output Bias, Impedance, and Termination Power Supply Decoupling, Grounding, and Layout Considerations Initial Power-Up Between Burst Operation Distortion, Adjacent Channel Power, and DOCSIS Noise and DOCSIS Evaluation Board Features and Operation Overshoot on PC Printer Ports Transformer and Diplexer Differential Inputs Single-Ended-to-Differential Input Differential Input Installing the Visual Basic Control Software Running the Software Controlling the Gain/Attenuation of the AD8325 Transmit Enable, Transmit Disable, and Sleep Memory Section EVALUATION BOARD FEATURES AND OPERATION EVALUATION BOARD BILL OF MATERIALS OUTLINE DIMENSIONS Revision History
Logic “1” Voltage 2.1 5.0 V Logic “0” Voltage 0 0.8 V Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN 0 20 nA Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN –600 –100 nA Logic “1” Current (VINH = 5 V) TXEN 50 190 mA Logic “0” Current (VINL = 0 V) TXEN –250 –30 mA Logic “1” Current (VINH = 5 V) SLEEP 50 190 mA Logic “0” Current (VINL = 0 V) SLEEP –250 –30 mA
TIMING REQUIREMENTS (Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.) Parameter Min Typ Max Unit
Clock Pulsewidth (TWH) 16.0 ns Clock Period (TC) 32.0 ns Setup Time SDATA vs. Clock (TDS) 5.0 ns Setup Time DATEN vs. Clock (TES) 15.0 ns Hold Time SDATA vs. Clock (TDH) 5.0 ns Hold Time DATEN vs. Clock (TEH) 3.0 ns Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF) 10 ns
TDS VALID DATA WORD G1 SDATA VALID DATA WORD G2 MSB. .LSB TC TWH CLK TES TEH 8 CLOCK DATEN CYCLES GAIN TRANSFER (G1) GAIN TRANSFER (G2) TOFF TXEN TGS TON ANALOG OUTPUT SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Timing
VALID DATA BIT SDATA MSB MSB-1 MSB-2 TDS TDH CLK
Figure 3. SDATA Timing REV. A –3– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS LOGIC INPUTS TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics APPLICATIONS General Application Operational Description SPI Programming and Gain Adjustment Input Bias, Impedance, and Termination Output Bias, Impedance, and Termination Power Supply Decoupling, Grounding, and Layout Considerations Initial Power-Up Between Burst Operation Distortion, Adjacent Channel Power, and DOCSIS Noise and DOCSIS Evaluation Board Features and Operation Overshoot on PC Printer Ports Transformer and Diplexer Differential Inputs Single-Ended-to-Differential Input Differential Input Installing the Visual Basic Control Software Running the Software Controlling the Gain/Attenuation of the AD8325 Transmit Enable, Transmit Disable, and Sleep Memory Section EVALUATION BOARD FEATURES AND OPERATION EVALUATION BOARD BILL OF MATERIALS OUTLINE DIMENSIONS Revision History