Datasheet AD8325 (Analog Devices) - 8

AD8325 Output Bias, Impedance, and Termination
input and output traces should be kept as short and symmetrical The differential output pins V as possible. In addition, the input and output traces should be OUT+ and VOUT– are also biased to a dc level of approximately V kept far apart in order to minimize coupling (crosstalk) through CC/2. Therefore, the outputs should be ac-coupled before being applied to the load. This is accomplished the board. Following these guidelines will improve the overall with a 1:1 transformer as seen in the typical applications circuit performance of the AD8325 in all applications. of Figure 6. The transformer also converts the output signal
Initial Power-Up
from differential to single-ended, while maintaining a proper When the 5 V supply is first applied to the VCC pins of the impedance match to the line. The differential output impedance AD8325, the gain setting of the amplifier is indeterminate. of the AD8325 is internally maintained at 75 W, regardless of Therefore, as power is first applied to the amplifier, the TXEN whether the amplifier is in transmit enable mode (TXEN = 1) pin should be held low (Logic 0) thus preventing forward signal or transmit disable mode (TXEN = 0). If the output signal is transmission. After power has been applied to the amplifier, the being evaluated on standard 50 W test equipment, a 75 W to 50 W gain can be set to the desired level by following the procedure in pad must be used to provide the test circuit with the correct the SPI Programming and Gain Adjustment section. The TXEN impedance match. pin can then be brought from Logic 0 to 1, enabling forward
Power Supply Decoupling, Grounding, and Layout
signal transmission at the desired gain level.
Considerations Between Burst Operation
Careful attention to printed circuit board layout details will The asynchronous TXEN pin is used to place the AD8325 into prevent problems due to associated board parasitics. Proper RF “Between Burst” mode while maintaining a differential output design techniques are mandatory. The 5 V supply power should be impedance of 75 W. Applying a Logic 0 to the TXEN pin acti­ delivered to each of the VCC pins via a low impedance power bus vates the on-chip reverse amplifier, providing a 74% reduction to ensure that each pin is at the same potential. The power bus in consumed power. The supply current is reduced from approxi­ should be decoupled to ground with a 10 mF tantalum capacitor mately 133 mA to approximately 35 mA. In this mode of located in close proximity to the AD8325. In addition to the operation, between burst noise is minimized and the amplifier 10 mF capacitor, each VCC pin should be individually decoupled to can no longer transmit in the upstream direction. In addition to ground with a 0.1 mF ceramic chip capacitor located as close to the TXEN pin, the AD8325 also incorporates an asynchronous the pin as possible. The pin labeled BYP (Pin 21) should also be SLEEP pin, which may be used to place the amplifier in a high decoupled with a 0.1 mF capacitor. The PCB should have a low- output impedance state and further reduce the supply current to impedance ground plane covering all unused portions of the approximately 4 mA. Applying a Logic 0 to the SLEEP pin component side of the board, except in the area of the input and places the amplifier into SLEEP mode. Transitioning into or output traces (see Figure 10). It is important that all of the out of SLEEP mode will result in a transient voltage at the output AD8325’s ground pins are connected to the ground plane to of the amplifier. Therefore, use only the TXEN pin for DOCSIS ensure proper grounding of all internal nodes. The differential compliant “Between Burst” operation.
5V 10
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F 25V AD8325 TSSOP 0.1
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F V DATEN IN– DATEN GND11 0.1
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F SDATA SDATA VCC6 Z CLK CLK V IN = 150
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IN– 165
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0.1
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F GND1 VIN+ V 0.1
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F CC GND10 TXEN TXEN VCC5 VIN+ SLEEP GND9 0.1
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F 0.1
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F GND2 BYP 0.1
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F VCC1 VCC4 SLEEP VCC2 VCC3 0.1
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F GND3 GND8 0.1
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F GND4 GND7 GND5 GND6 OUT– OUT+ 0.1
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F TOKO 617DB-A0070 TO DIPLEXER ZIN = 75
� Figure 6. Typical Applications Circuit –8– REV. A Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS LOGIC INPUTS TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics APPLICATIONS General Application Operational Description SPI Programming and Gain Adjustment Input Bias, Impedance, and Termination Output Bias, Impedance, and Termination Power Supply Decoupling, Grounding, and Layout Considerations Initial Power-Up Between Burst Operation Distortion, Adjacent Channel Power, and DOCSIS Noise and DOCSIS Evaluation Board Features and Operation Overshoot on PC Printer Ports Transformer and Diplexer Differential Inputs Single-Ended-to-Differential Input Differential Input Installing the Visual Basic Control Software Running the Software Controlling the Gain/Attenuation of the AD8325 Transmit Enable, Transmit Disable, and Sleep Memory Section EVALUATION BOARD FEATURES AND OPERATION EVALUATION BOARD BILL OF MATERIALS OUTLINE DIMENSIONS Revision History