Datasheet AD8488 (Analog Devices)

128-Channel Digital X-Ray Analog Front End Data Sheet AD8488 FEATURES GENERAL DESCRIPTION 128 integrator channels
The AD8488 is a 128-channel, analog front end (AFE) designed for
Correlated double sample error correction (CDS)
use in high performance digital X-ray systems. The analog channels
Corrects for VOS and LF noise
consist of an integrator followed by a gain selectable single-ended
Power consumption per channel
to low impedance differential output. The analog channel converts
Normal: 11 mW
the charge acquired by X-ray or photodiode detectors to a voltage.
Low power: 4 mW
The channels are composed of CMOS transistors, using typical
Low input leakage current: −1.5 pA typical
high input impedance CMOS gates. The integrators generate charge
Low input referred noise (QNI): 993 e−rms typical
dependent voltages using a range of selectable capacitance values that
Linearity error: 0.03% typical
accommodate a broad range of input charge values. The integrators
Compact 17 mm × 17 mm BGA
are followed by single-ended input to differential output voltage
Selectable filter time constants
amplifiers where offset and low frequency noise voltages are
4 selectable input charge ranges
subtracted from the input voltages. A 128:1 channel differential
10 selectable gain ranges
MUX follows the buffers and drives the analog output buffer.
APPLICATION
Switch drivers and certain digital timing functions are included, and all are mounted on a 255-lead BGA substrate. Charge conversion
High performance digital X-ray systems
for all 128 channels is simultaneous followed by a sequential voltage
Medical X-ray
output read of the channels using a 7-bit address code. The sequence
Security (baggage scanner) systems
occurs twice, sampling all 128 channels. Logic control inputs, CS_A and CS_B, select the lower and upper 64 blocks of the channel addresses. The AD8488 is packaged in a 17 mm × 17 mm, 255-lead, RoHS- compliant bal grid array (BGA). The operating temperature range is 0°C to 85°C ambient.
FUNCTIONAL BLOCK DIAGRAM OUTPUT BUFFER CHARGE CONVERSION AMPLIFIER 128 CHANNELS DIFFERENTIAL OUTHI OUTPUT IN0:127 MULTIPLEXER INT INT LPF GAIN AMPLIFIER 128:1 OUTLO ANALOG INPUTS 128 VREF TIMING AND CONTROL 7 CONTROL REGISTER MUX SELECTOR R T T PW IRS RS OLD G H 2 4 2 7 TIMING SIGNALS 1 L L3 L1 T6 B K RB T ST Na Nb B_b E E E T S W CL 1S RS CS , FS O TS T CK_E CK_E CF O GN L0 B_a, 0, T E T0 L 0 CS E FS TS 1S SEL CF N G
001
CONTROL SIGNALS
09801- Figure 1.
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Document Outline Features Application General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Data Thermal Characterization ESD Caution Pin Configuration and Function Descriptions Signal Mnemonics Typical Performance Characteristics Theory of Operation Overview Analog Amplifier Troubleshooting Channels Timing Signals Timing Notes Applications Information Control Register Bit Maps Timing Diagrams Outline Dimensions Ordering Guide