Datasheet AD626 (Analog Devices) - 9

AD626 100 100 90 90 10 10 0% 0%
TPC 25. Settling Time. VS = +5 V, G = 10 TPC 26. Settling Time. VS = +5 V, G = 100 Figure 4 shows the main elements of the AD626. The signal in puts
ERROR OUT
at Pins 1 and 8 are fi rst applied to dual resistive at ten u a tors R1
10k
⍀
10k
⍀ through R4 whose purpose is to reduce the peak com mon-mode
2k
⍀ voltage at the input to the preamplifi er—a feed back stage based
+VS
on the very low drift op amp A1. This allows the dif feren tial
10k
⍀ input voltage to be accurately amplifi ed in the pres ence of large
INPUT 20V p–p
common-mode volt ag es six times greater than that which can be
1k
⍀
AD626
tol er at ed by the actual input to A1. As a re sult, the in put CMR ex tends to six times the quantity (VS – 1 V). The over all common - mode error is min i mized by precise laser-trimming of R3 and R4,
–V
thus giving the AD626 a common-mode re jec tion ra tio (CMRR)
S
of at least 10,000:1 (80 dB). Figure 3. Settling Time Test Circuit To minimize the effect of spurious RF signals at the inputs due to rectifi cation at the input to A1, small fi lter capacitors C1 and C2
THEORY OF OPERATION
are included. The AD626 is a differential amplifi er con sist ing of a precision bal anced attenuator, a very low drift preamplifi er (A1), and an The output of A1 is connected to the in put of A2 via a 100 k⍀ out put buffer amplifi er (A2). It has been designed so that small (R12) resistor to facilitate the low-pass fi ltering of the sig nal of differential signals can be accurately am pli fi ed and fi ltered in the in ter est (see Low-Pass Filtering section). presence of large common -mode voltages (VCM), without the use The 200 k⍀ input impedance of the AD626 requires that the source of any other active components. re sis tance driving this amplifi er be low in val ue (<1 k⍀)—this is
+VS FILTER C1 AD626 5pF R1 200k
⍀
R12 +IN 100k
⍀
A1 –IN A2 OUT R2 C2 200k
⍀
5pF R17 R3 R4 95k
⍀
41k
⍀
41k
⍀
R15 R9 10k
⍀
10k
⍀
R5 4.2k
⍀
R11 R6 R7 R8 R10 R14 R13 10k
⍀
500
⍀
500
⍀
10k
⍀
10k
⍀
555
⍀
10k
⍀
GND GAIN = 100 –VS
Figure 4. Simplifi ed Schematic REV. D –9– Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION CONECTION DIAGRAM SPECIFICATIONS SINGLE SUPPLY DUAL SUPPLY ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Typical Performance Characteristics THEORY OF OPERATION ADJUSTING THE GAIN OF THE AD626 SINGLE-POLE LOW-PASS FILTERING CURRENT SENSOR INTERFACE BRIDGE APPLICATION OUTLINE DIMENSIONS Revision History