Datasheet AD5522 (Analog Devices) - 9

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Data Sheet AD5522 Parameter Min Typ1 Max Unit Test Conditions/Comments
GUARDx PIN Output Voltage Span 22.5 V Output Offset −10 +10 mV Short-Circuit Current −15 +15 mA Maximum Load Capacitance2 100 nF Output Impedance 85 Ω Tristate Leakage Current2 −30 +30 nA When guard amplifier is disabled Slew Rate2 5 V/μs CLOAD = 10 pF Alarm Activation Time2 200 μs Alarm delayed to eliminate false alarms FORCE AMPLIFIER2 Slew Rate 0.4 V/μs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF Gain Bandwidth 1.3 MHz CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF Max Stable Load Capacitance 10,000 pF CCOMPx = 100 pF, larger CLOAD requires larger CCOMP capacitor 100 nF CCOMPx = 1 nF, larger CLOAD requires larger CCOMP capacitor FV SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; measured from SYNC rising edge, clamps on ±80 mA Range 22 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±2 mA Range 24 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±200 µA Range 40 80 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±20 µA Range 300 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±5 µA Range 1400 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF MI SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; driven from force amplifier in FV mode, so includes FV settling time, measured from SYNC rising edge, clamps on ±80 mA Range 22 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±2 mA Range 24 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±200 µA Range 60 100 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±20 µA Range 462 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±5 µA Range 1902 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF FI SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; measured from SYNC rising edge, clamps on ±80 mA Range 24 55 µs CCOMPx = 100 pF, CLOAD = 200 pF ±2 mA Range 24 60 µs CCOMPx = 100 pF, CLOAD = 200 pF ±200 µA Range 50 120 µs CCOMPx = 100 pF, CLOAD = 200 pF ±20 µA Range 450 µs CCOMPx = 100 pF, CLOAD = 200 pF ±5 µA Range 2700 µs CCOMPx = 100 pF, CLOAD = 200 pF MV SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; driven from force amplifier in FV mode, so includes FV settling time, measured from SYNC rising edge, clamps on ±80 mA Range 24 55 µs CCOMPx = 100 pF, CLOAD = 200 pF ±2 mA Range 24 60 µs CCOMPx = 100 pF, CLOAD = 200 pF ±200 µA Range 50 120 µs CCOMPx = 100 pF, CLOAD = 200 pF ±20 µA Range 450 µs CCOMPx = 100 pF, CLOAD = 200 pF ±5 µA Range 2700 µs CCOMPx = 100 pF, CLOAD = 200 pF DAC SPECIFICATIONS Resolution 16 Bits Output Voltage Span2 22.5 V VREF = 5 V, within a range of −16.25 V to +22.5 V Differential Nonlinearity2 −1 +1 LSB Guaranteed monotonic by design over temperature COMPARATOR DAC DYNAMIC SPECIFICATIONS2 Output Voltage Settling Time 1 µs 500 mV change to ±½ LSB Slew Rate 5.5 V/µs Digital-to-Analog Glitch Energy 20 nV-sec Glitch Impulse Peak Amplitude 10 mV REFERENCE INPUT VREF DC Input Impedance 1 100 MΩ VREF Input Current −10 +0.03 +10 µA VREF Range2 2 5 V Rev. F | Page 9 of 64 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications Timing Characteristics Circuit and Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Force Amplifier Comparators Clamps Current Range Selection High Current Ranges Measure Current Gains VMID Voltage Choosing Power Supply Rails Measure Output (MEASOUTx Pins) Device Under Test Ground (DUTGND) Guard Amplifier Compensation Capacitors System Force and Sense Switches Temperature Sensor DAC Levels Offset DAC Gain and Offset Registers Cached X2 Registers Gain and Offset Registers for the FIN DAC Gain and Offset Registers for the Comparator DACs Gain and Offset Registers for the Clamp DACs Reference Voltage (VREF) Reference Selection Reference Selection Example Calibration Reducing Zero-Scale Error Reducing Gain Error Calibration Example Additional Calibration System Level Calibration Circuit Operation Force Voltage (FV) Mode Force Current (FI) Mode Serial Interface SPI Interface LVDS Interface Serial Interface Write Mode RESETB Function BUSYB and LOADB Functions Register Update Rates Register Selection Readback Control, RD/WRB PMU Address Bits: PMU3, PMU2, PMU1, PMU0 NOP (No Operation) Reserved Commands Write System Control Register Write PMU Register Write DAC Register DAC Addressing Read Registers Readback of System Control Register Readback of PMU Register Readback of Comparator Status Register Readback of Alarm Status Register Readback of DAC Register Applications Information Power-On Default Setting Up the Device on Power-On Changing Modes Required External Components Power Supply Decoupling Power Supply Sequencing Typical Application for the AD5522 Outline Dimensions Ordering Guide