Datasheet AD5560 (Analog Devices)

1.2 A Programmable Device Power Supply with Integrated 16-Bit Level Setting DACs Data Sheet AD5560 FEATURES On-chip comparators Programmable device power supply (DPS) Gangable for higher current FV, MI, MV, FNMV functions Guard amplifier 5 internal current ranges (on-chip R ) System PMU connections SENSE ±5 µA, ±25 µA, ±250 µA, ±2.5 mA, ±25 mA Current clamps 2 external high current ranges (external R ) Die temperature sensor and shutdown feature SENSE EXTFORCE1: ±1.2 A maximum On-chip diode thermal array EXTFORCE2: ±500 mA maximum Diagnostic register allows access to internal nodes Integrated programmable levels Open-drain alarm flags (temperature, current clamp, Kelvin All 16-bit DACs: force DAC, comparator DACs, clamp DACs, alarm) offset DAC, OSD DAC, DGS DAC SPI-/MICROWIRE-/DSP-compatible interface Programmable Kelvin clamp and alarm 64-lead (10 mm × 10 mm) TQFP with exposed pad (on top) Offset and gain correction registers on-chip 72-ball (8 mm × 8 mm) flip-chip BGA Ramp mode on force DAC for power supply slewing APPLICATIONS Programmable slew rate feature, 1 V/μs to 0.3 V/μs Automatic test equipment (ATE) DUTGND Kelvin sense and alarm Device power supply 25 V FV span with asymmetrical operation within −22 V/+25 V GENERAL DESCRIPTION
The AD5560 is a high performance, highly integrated device dissipation. Current ranges in excess of ±1.2 A or at high power supply consisting of programmable force voltages and current and high voltage combinations can be achieved by measure ranges. This part includes the required DAC levels to paralleling or ganging multiple DPS devices. Open-drain set the programmable inputs for the drive amplifier, as well as alarm outputs are provided in the event of overcurrent, clamping and comparator circuitry. Offset and gain correction overtemperature, or Kelvin alarm on either the SENSE or is included on-chip for DAC functions. A number of program- DUTGND line. mable measure current ranges are available: five internal fixed The DPS functions are controlled via a simple 3-wire serial ranges and two external customer-selectable ranges (EXTFORCE1 interface compatible with SPI, QSPI™, MICROWIRE™, and DSP and EXTFORCE2) that can supply currents up to ±1.2 A and interface standards running at clock speeds of up to 50 MHz. ±500 mA, respectively. The voltage range possible at this high current level is limited by headroom and the maximum power
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE