Datasheet AD5560 (Analog Devices) - 3

制造商Analog Devices
描述1.2 A Programmable Device Power Supply with Integrated 16-Bit Level Setting DACs
页数 / 页66 / 3 — Data Sheet. AD5560. REVISION HISTORY 5/2016—Rev. D to Rev. E. 9/2009—Rev. …
修订版E
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Data Sheet. AD5560. REVISION HISTORY 5/2016—Rev. D to Rev. E. 9/2009—Rev. A to Rev. B. 8/2012—Rev. C to Rev. D

Data Sheet AD5560 REVISION HISTORY 5/2016—Rev D to Rev E 9/2009—Rev A to Rev B 8/2012—Rev C to Rev D

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Data Sheet AD5560 REVISION HISTORY 5/2016—Rev. D to Rev. E 9/2009—Rev. A to Rev. B
Changes to Figure 1... 4 Changes to Table 1, Measure Current and Measure Voltage Changes to High Current Ranges Section ... 31 Parameters .. 6 Added Calibration Section, Reducing Zero-Scale Error Section, Changes to Die Temperature Sensor and Thermal Reducing Gain Error Section, Calibration Example Section, Shutdown Section ... 31 Additional Calibration Section, and System Level Calibration Changes to Table 10 and Table 11 ... 32 Section .. 41 Changes to Table 18, Bit 15 .. 45 Added Figure 58; Renumbered Sequentially ... 42 Changes to Table 23, Bits[15:12] ... 50 Changes to Table 25 .. 57 Changes to Table 25 .. 54
8/2012—Rev. C to Rev. D 12/2008—Rev. 0 to Rev. A
Added 72-Ball Flip-Chip BGA (Throughout) ... 1 Changes to Figure 1 .. 4 Added Figure 7 and Table 5 (Renumbered Sequential y) .. 18 Changes to Table 1 .. 4 Added Applications Information Section .. 62 Changes to Table 2 .. 13 Updated Outline Dimensions .. 64 Changes to Table 3 .. 15 Changes to Ordering Guide ... 65 Changes to Open-Sense Detect (OSD) Alarm and Clamp ... 27 Changes to Figure 53 .. 30
10/2010—Rev. B to Rev. C
Change to gm Maximum Rating, Table 13 ... 34 Changes to Force Output Voltage Parameter and Load Transient Changes to Table 19 .. 46 Response Parameter, Table 1 .. 5 Changes to Bit 7, Bit 8 Functions, Table 21 ... 48 Changes to Figure 52 .. 29 Changes to Power Supply Decoupling Section ... 59 Changes to Table 9 .. 32
11/2008—Revision 0: Initial Version
Rev. E | Page 3 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE