Datasheet AD5560 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 1.2 A Programmable Device Power Supply with Integrated 16-Bit Level Setting DACs |
| 页数 / 页 | 66 / 7 — Data Sheet. AD5560. Parameter. Min. Typ. Max. Unit. Test … |
| 修订版 | E |
| 文件格式/大小 | PDF / 2.1 Mb |
| 文件语言 | 英语 |
Data Sheet. AD5560. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments
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Data Sheet AD5560 Parameter Min Typ Max Unit Test Conditions/Comments
MEASOUT Gain = 0.2 Linearity Error −5.5 +5.5 mV Referred to MV input, nominal supply (±16.5 V, 0x8000 offset DAC) −9 +24 mV Referred to MV input, low supply (−25 V/+8 V, 0xD4EB offset DAC) −4 +13 mV Referred to MV input, high supply (−5 V/+28 V, 0xD1D offset DAC) Offset Error −30 +20 mV Referred to MV output Offset Error Tempco1 10 µV/°C Standard deviation = 12 µV/°C, referred to MV output NSD1 50 nV/√Hz At 1 kHz, at MEASOUT, inputs grounded COMBINED LEAKAGE Includes SYS_SENSE, SYS_FORCE, EXTFORCE1, EXTFORCE2, EXTMEASIH1, EXTMEASIH2, EXTMEASIL, FORCE, and SENSE; measured with PD = 1, SW-INH = 0 (power up and tristate) Leakage Current −37.5 +37.5 nA −30 +30 nA TJ = 25°C to 70°C Leakage Current Tempco1 ±0.1 ±0.4 nA/°C SENSE INPUT Leakage Current −2.5 +2.5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.01 nA/°C Pin Capacitance1 10 pF EXTMEASIH1, EXTMEASIH2, EXTMEASIL Leakage Current −2.5 +2.5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.01 nA/°C Pin Capacitance1 5 pF FORCE OUTPUT, FORCE Maximum Current Drive1 −30 +30 mA Leakage Current −10 +10 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.03 nA/°C Pin Capacitance1 120 pF EXTFORCE1 OUTPUTS Maximum Current Drive1 −1200 +1200 mA Set with external sense resistor, limited by headroom and power dissipation Leakage Current −7.5 +7.5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.03 ±0.06 nA/°C Pin Capacitance1 275 pF EXTFORCE2 OUTPUTS Maximum Current Drive1 −500 +500 mA Set with external sense resistor, limited by headroom and power dissipation Leakage Current −5 +5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.02 ±0.05 nA/°C Pin Capacitance1 100 pF SYS_SENSE Voltage Range AVSS AVDD V Leakage Current −2.5 +2.5 nA SYS_SENSE high-Z, force amplifier inhibited Leakage Current Tempco1 ±0.005 ±0.025 nA/°C Path On Resistance 280 Ω AVDD = 16.5 V, AVSS = −16.5 V Pin Capacitance1 5 pF Rev. E | Page 7 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD5560 Parameter Min Typ Max Unit Test Conditions/Comments
MEASOUT Gain = 0.2 Linearity Error −5.5 +5.5 mV Referred to MV input, nominal supply (±16.5 V, 0x8000 offset DAC) −9 +24 mV Referred to MV input, low supply (−25 V/+8 V, 0xD4EB offset DAC) −4 +13 mV Referred to MV input, high supply (−5 V/+28 V, 0xD1D offset DAC) Offset Error −30 +20 mV Referred to MV output Offset Error Tempco1 10 µV/°C Standard deviation = 12 µV/°C, referred to MV output NSD1 50 nV/√Hz At 1 kHz, at MEASOUT, inputs grounded COMBINED LEAKAGE Includes SYS_SENSE, SYS_FORCE, EXTFORCE1, EXTFORCE2, EXTMEASIH1, EXTMEASIH2, EXTMEASIL, FORCE, and SENSE; measured with PD = 1, SW-INH = 0 (power up and tristate) Leakage Current −37.5 +37.5 nA −30 +30 nA TJ = 25°C to 70°C Leakage Current Tempco1 ±0.1 ±0.4 nA/°C SENSE INPUT Leakage Current −2.5 +2.5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.01 nA/°C Pin Capacitance1 10 pF EXTMEASIH1, EXTMEASIH2, EXTMEASIL Leakage Current −2.5 +2.5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.01 nA/°C Pin Capacitance1 5 pF FORCE OUTPUT, FORCE Maximum Current Drive1 −30 +30 mA Leakage Current −10 +10 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.03 nA/°C Pin Capacitance1 120 pF EXTFORCE1 OUTPUTS Maximum Current Drive1 −1200 +1200 mA Set with external sense resistor, limited by headroom and power dissipation Leakage Current −7.5 +7.5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.03 ±0.06 nA/°C Pin Capacitance1 275 pF EXTFORCE2 OUTPUTS Maximum Current Drive1 −500 +500 mA Set with external sense resistor, limited by headroom and power dissipation Leakage Current −5 +5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.02 ±0.05 nA/°C Pin Capacitance1 100 pF SYS_SENSE Voltage Range AVSS AVDD V Leakage Current −2.5 +2.5 nA SYS_SENSE high-Z, force amplifier inhibited Leakage Current Tempco1 ±0.005 ±0.025 nA/°C Path On Resistance 280 Ω AVDD = 16.5 V, AVSS = −16.5 V Pin Capacitance1 5 pF Rev. E | Page 7 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE