Datasheet AD5560 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 1.2 A Programmable Device Power Supply with Integrated 16-Bit Level Setting DACs |
| 页数 / 页 | 66 / 10 — AD5560. Data Sheet. Parameter. Min. Typ. Max. Unit. Test … |
| 修订版 | E |
| 文件格式/大小 | PDF / 2.1 Mb |
| 文件语言 | 英语 |
AD5560. Data Sheet. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments
该数据表的模型线
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AD5560 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
REFERENCE INPUT VREF DC Input Impedance 1 MΩ Typically 100 MΩ VREF Input Current −10 +10 µA Per input; typically ±30 nA VREF Range1 2 5 V COMPARATOR Measured directly at comparator; does not include measure block errors Error −7 +7 mV Uncalibrated VOLTAGE COMPARATOR With respect to the measured voltage Propagation Delay1 0.25 µs Error1 −12 +12 mV Uncalibrated CURRENT COMPARATOR Propagation Delay1 0.25 1 µs Error1 −1.5 +1.5 % Of programmed current range, uncalibrated MEASURE OUTPUT, MEASOUT Measure Output Voltage Span1 −12.81 +12.81 V MEASOUT gain = 1, VREF = 5 V, offset DAC = 0x8000 Measure Output Voltage Span1 −6.405 +6.405 V MEASOUT gain = 1, VREF = 2.5 V Measure Output Voltage Span1 0 5.125 V MEASOUT gain = 0.2, VREF = 5 V, offset DAC = 0x8000 Measure Output Voltage Span1 0 2.56 V MEASOUT gain = 0.2, VREF = 2.5 V Measure Pin Output Impedance 115 Ω Output Leakage Current −100 +100 nA When HW_INH is low Output Capacitance1 5 pF Short-Circuit Current1 −10 +10 mA OPEN-SENSE DETECT/CLAMP/ALARM Measurement Accuracy −200 +200 mV Clamp Accuracy 600 900 mV Alarm Delay1 50 μs DUTGND Voltage Range1 −1 +1 V Pull-Up Current +50 +70 μA Pull-up for purpose of detecting open circuit on DUTGND, can be disabled Leakage Current −1 +1 μA When pull-up disabled, DGS DAC = 0x3333 (1 V with VREF = 5 V); if DUTGND voltage is far away from one of comparator thresholds, more leakage may be present Trip Point Accuracy −30 +10 mV Alarm Delay1 50 μs GUARD AMPLIFIER Voltage Range1 AVSS + 2.25 AVDD − 2.25 V Voltage Span1 25 V Output Offset −10 +10 mV Short-Circuit Current1 −20 +20 mA Load Capacitance1 100 nF Output Impedance 100 Ω Alarm Delay1 200 μs If it moves 100 mV away from input level DIE TEMPERATURE SENSOR Accuracy1 −10 +10 % Relative to a temperature change Output Voltage at 25°C 1.54 V Output Scale Factor1 4.7 mV/°C Output Voltage Range1 1 2 V Rev. E | Page 10 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE
AD5560 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
REFERENCE INPUT VREF DC Input Impedance 1 MΩ Typically 100 MΩ VREF Input Current −10 +10 µA Per input; typically ±30 nA VREF Range1 2 5 V COMPARATOR Measured directly at comparator; does not include measure block errors Error −7 +7 mV Uncalibrated VOLTAGE COMPARATOR With respect to the measured voltage Propagation Delay1 0.25 µs Error1 −12 +12 mV Uncalibrated CURRENT COMPARATOR Propagation Delay1 0.25 1 µs Error1 −1.5 +1.5 % Of programmed current range, uncalibrated MEASURE OUTPUT, MEASOUT Measure Output Voltage Span1 −12.81 +12.81 V MEASOUT gain = 1, VREF = 5 V, offset DAC = 0x8000 Measure Output Voltage Span1 −6.405 +6.405 V MEASOUT gain = 1, VREF = 2.5 V Measure Output Voltage Span1 0 5.125 V MEASOUT gain = 0.2, VREF = 5 V, offset DAC = 0x8000 Measure Output Voltage Span1 0 2.56 V MEASOUT gain = 0.2, VREF = 2.5 V Measure Pin Output Impedance 115 Ω Output Leakage Current −100 +100 nA When HW_INH is low Output Capacitance1 5 pF Short-Circuit Current1 −10 +10 mA OPEN-SENSE DETECT/CLAMP/ALARM Measurement Accuracy −200 +200 mV Clamp Accuracy 600 900 mV Alarm Delay1 50 μs DUTGND Voltage Range1 −1 +1 V Pull-Up Current +50 +70 μA Pull-up for purpose of detecting open circuit on DUTGND, can be disabled Leakage Current −1 +1 μA When pull-up disabled, DGS DAC = 0x3333 (1 V with VREF = 5 V); if DUTGND voltage is far away from one of comparator thresholds, more leakage may be present Trip Point Accuracy −30 +10 mV Alarm Delay1 50 μs GUARD AMPLIFIER Voltage Range1 AVSS + 2.25 AVDD − 2.25 V Voltage Span1 25 V Output Offset −10 +10 mV Short-Circuit Current1 −20 +20 mA Load Capacitance1 100 nF Output Impedance 100 Ω Alarm Delay1 200 μs If it moves 100 mV away from input level DIE TEMPERATURE SENSOR Accuracy1 −10 +10 % Relative to a temperature change Output Voltage at 25°C 1.54 V Output Scale Factor1 4.7 mV/°C Output Voltage Range1 1 2 V Rev. E | Page 10 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE