Datasheet LTC3315B (Analog Devices) - 10

link to page 12 LTC3315B
OPERATION Buck Switching Regulators
there is a 400µs (typical) delay while internal circuitry The LTC3315B is a 5V dual 2A monolithic, constant fre- powers up followed by a 100µs (typical) no start time quency, peak current mode step-down DC/DC converter. before switching commences and the soft-start ramp The synchronous buck switching regulators are internally begins. If a second buck is then enabled, it will also have compensated and require only external feedback resistors a 100µs (typical) no start time. If the second buck is to set the output voltage. enabled within 400µs of the first buck, it will wait until the expiry of the 400µs to begin its no start time. An internal oscillator, which can be externally synchro- nized, turns on the internal PMOS power switch at the The buck switching regulators are switched 180° out of beginning of each clock cycle. Current in the inductor phase with respect to each other. The phase determines ramps up until the PMOS current comparator trips and the fixed edge of the switching sequence, which is when turns off the PMOS. The peak inductor current, I the PMOS turns on. The PMOS off (NMOS on) phase is PEAK, at which the PMOS turns off is controlled by an internal V subject to the regulated duty cycle of each buck. C voltage which the error amplifier regulates by compar-
Mode Selection
ing the voltage on the feedback (FB) pin with an internal 500mV reference. An increase in the load current causes The buck switching regulators operate in three different a reduction in the feedback voltage relative to the refer- modes set by the MODE/SYNC pin: pulse skipping mode ence, causing the error amplifier to raise the VC voltage (when the MODE/SYNC pin is set low), forced continuous (and IPEAK) until the average inductor current matches the PWM mode (when the MODE/SYNC pin is floating), and new load current. When the PMOS turns off, the NMOS Burst Mode (when the MODE/SYNC pin is set high). The turns on and ramps down the inductor current for the MODE/SYNC pin sets the operating mode for both buck remainder of the clock cycle or, if in pulse skipping mode switching regulators. or Burst Mode, until the inductor current falls to zero. If In pulse skipping mode, the oscillator operates continu- an overload condition results in excessive current flowing ously and positive SW transitions are aligned to the clock. through the NMOS, the next clock cycle will be skipped Negative inductor current is disallowed and during light until the current returns to a safe level. loads switch pulses are skipped to regulate the output. Each buck switching regulator has its own SW, FB, and In forced continuous mode, the oscillator runs continu- EN pins. The buck input supplies are internally connected, ously, no pulses are skipped, and switching occurs in but each VIN pin should have its own input bypass capaci- every cycle. To maintain regulation, the inductor current tor (see Applications Information). The enable pins have is allowed to reverse under light load conditions. This precision 400mV thresholds which may be used to pro- mode allows the buck to run at a fixed frequency with vide event-based power-up sequencing by connecting minimal output ripple. In forced continuous mode if the the enable pin to the output of another buck through a inductor current reaches –1A (typical, 1A into the SW pin) resistor divider. If the EN pin of a buck is low, that buck is the NMOS will turn off for the remainder of the cycle to in shutdown and in a low quiescent current state. If both limit the current. EN pins are low, both bucks are in shutdown, the SW pins are high impedance, and the quiescent current of the In Burst Mode operation, at light loads, the output capaci- LTC3315B is 1µA (typical). If either EN pin is above the tor is charged to a voltage slightly higher than its regu- enable threshold of 400mV its respective buck is enabled. lation point. The regulator then goes into a sleep state, during which time the output capacitor provides the load Both buck regulators have forward and reverse inductor current. In sleep most of the regulator’s circuitry is pow- current limiting, soft-start to limit inrush current during ered down, helping to conserve input power. When the start-up, and short-circuit protection. When both bucks output voltage drops below its programmed value, the cir- are disabled and either buck is subsequently enabled, cuitry is powered back on and another burst cycle begins. Rev. 0 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts