Datasheet ADP5138 (Analog Devices) - 3

Data Sheet ADP5138 FUNCTIONAL BLOCK DIAGRAM CHANNEL 1: BUCK REGULATOR 1 PVIN1 ACS1 HIGH-SIDE CURRENT SENSE I OCP LIM SLOPE RAMP PVIN1 SOFT DRIVER START VREF CMP1 EA1 FB1 DIVIDER SW1 TSD CONTROL 110% × VREF LOGIC AND MOSFET PVIN1 DRIVER PGOOD1 WITH DRIVER ANTICROSS 95% × VREF UVLO PROTECTION PGND1 1.2V OVLO EN_DELAY LOW-SIDE EN1 EN1_BUF CLK1 CURRENT SENSE FB2 PVIN2 CHANNEL 2: BUCK REGULATOR 2 SW2 EN2 PGND2 FB3 PVIN3 CHANNEL 3: BUCK REGULATOR 3 SW3 EN3 PGND3 FB4 PVIN4 CHANNEL 4: BUCK REGULATOR 4 SW4 EN4 PGND4 CHANNEL 5: LDO PVIN5 VOUT5 VREF 1.2V EN5_BUF EN_DELAY R EA5 EN5 IDE FB5 UVLO 110% × VREF LDO V CONTROL DI OVLO TSD PGOOD5 95% × VREF EN1_BUF COMMON BLOCK CLK1 EN2_BUF SLOPE RAMP1 EN3_BUF EN_SYS EN4_BUF CLK2 EN5_BUF SLOPE RAMP2 OSC SYNC 2.8V CLK3 UVLO SLOPE RAMP3 AVIN 4.2V VIN_OK CLK4 UVM SLOPE RAMP4 5.8V OVLO POR TSD POR DELAY TSD THERMAL TIME AND GND CONTROL LOGIC PGOOD1 EN1_BUF PGOOD2 EN2_BUF VOUT_OK PGOOD3 EN3_BUF PGOOD4 EN4_BUF PGOOD5 EN5_BUF ADP5138
002 16669- Figure 2. Rev. A | Page 3 of 23 Document Outline Features Applications Typical Application Circuit General Description Revision History Functional Block Diagram Specifications Buck Regulator Specifications LDO Regulator Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Control Scheme Precision Enable and Shutdown Oscillator and Phase Shift Synchronization Input Overvoltage Lockout (OVLO) Input Undervoltage Monitor (UVM) Input Undervoltage Lockout (UVLO) Output Voltage Power-Good Power-On Reset (POR) Soft Start and Power-Up Sequence Current-Limit and Short-Circuit Protection Active Output Discharge Thermal Shutdown Applications Information Input Capacitor Selection Output Voltage Setting Inductor Selection Output Capacitor Selection Application Circuit Factory-Programmable Options Outline Dimensions Ordering Guide Automotive Products