Datasheet ADP5014 (Analog Devices)

Integrated Power Solution with Quad Low Noise Buck Regulators Data Sheet ADP5014 FEATURES TYPICAL APPLICATION CIRCUIT Input voltage range: 2.75 V to 6.0 V ADP5014 VREF Programmable output voltage range: 0.5 V to 0.9 × PVINx RRT RT C1 OSC REF Low output noise: ~25 μV rms when VOUT ≤ VREF EN1/ENALL CFG1 ±1.0% output accuracy over full temperature range EN2/DL12 CFG2 EN3/UV LOGIC DECODER 500 kHz to 2.5 MHz adjustable switching frequency GPIO EN4/DL34 Power regulation AVIN FB1 Channel 1 and Channel 2: programmable 2 A/4 A sync 2.75V TO 6.0V PVIN1 SW1 buck regulators, or single 8 A output in parallel C2 CH 1 L1 PVIN1 VOUT1 VREF LOW-NOISE BUCK Channel 3 and Channel 4: programmable 1 A/2 A sync VSET1 (2A/4A) C3 PGND1 buck regulators, or single 4 A output in parallel COMP1 Flexible parallel operation Precision enable with 0.6 V threshold FB2 PVIN2 Manual or sequence mode for power-up and power-down C4 SW2 CH 2 L2 VOUT2 LOW-NOISE BUCK sequence VREFVSET2 (2A/4A) PGND2 C5 Selective FPWM or PSM operation mode COMP2 Precision undervoltage comparator Frequency synchronization input or output PVIN3 L3 SW3 VOUT3 Active output discharge switch C6 CH 3 FB3 C7 VREF Power-good flag on selective channels via factory fuse VSET3 LOW-NOISE BUCK (1A/2A) UVLO, OVP, OCP, and TSD protection PGND3 COMP3 40-lead, 6 mm × 6 mm LFCSP package −40°C to +125°C junction temperature PVIN4 L4 SW4 VOUT4 C8 FB4 C9 APPLICATIONS VREF CH 4 VSET4 LOW-NOISE BUCK (1A/2A) PGND4 RF transceiver, high speed analog-to-digital converter COMP4 (ADC)/digital-to-analog converter (DAC), mixed signal ASIC FPGA and processor applications
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AGND Security and surveillance EXPOSED PAD
15496-
Medical applications
Figure 1.
GENERAL DESCRIPTION
The ADP5014 combines four high performance, low noise The ADP5014 features two enable modes. The manual mode buck regulators in a 40-lead LFCSP package. Relying on its low has four individual precision enable pins to enable each output noise (~25 μV rms when VOUT ≤ VREF), the low noise regulator manually. Alternatively, the sequence mode has one buck regulator enables the powering up of the noise sensitive grouped precision enable signal with programmable power-up signal chain products. and power-down delay timers on each rail for specific rail All channels in the ADP5014 integrate high-side and low-side sequence requirements. power metal-oxide semiconductor field effect transistors The switching frequency of the ADP5014 can be programmed (MOSFET). Channel 1 and Channel 2 deliver a programmable or synchronized to an external clock from 500 kHz to 2.5 MHz. output current of 2 A or 4 A. Combining Channel 1 and The ADP5014 offers other key features like selective forced Channel 2 in a parallel configuration provides a single output pulse width modulation (FPWM)/power saving mode (PSM), with up to 8 A of current. an undervoltage output (UVO), active output discharge, and a Channel 3 and Channel 4 deliver a programmable output current power-good flag. Other safety features include input under- of 1 A or 2 A. Combining Channel 3 and Channel 4 in a parallel voltage lockout (UVLO), overvoltage protection (OVP), configuration can provide a single output with up to 4 A of overcurrent protection (OCP) and thermal shutdown (TSD). current.
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Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode FPWM and Automatic PWM/PSM Modes LOW NOISE ARCHITECTURE INTERNAL REFERENCE (VREF) ADJUSTABLE OUTPUT VOLTAGE FUNCTION CONFIGURATIONS (CFG1 AND CFG2) PARALLEL OPERATION MANUAL/SEQUENCE MODE Manual Mode (Precision Enable) Sequence Mode GENERAL PURPOSE INPUT/OUTPUT (GPIO) OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT POWER-GOOD FUNCTION UV COMPARATOR (SEQUENCE MODE ONLY) SOFT START STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLD BACK SHORT-CIRCUIT PROTECTION (SCP) OVERVOLTAGE PROTECTION UNDERVOLTAGE LOCKOUT ACTIVE OUTPUT DISCHARGE SWITCH THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CONFIGUATIONS (CFG1 AND CFG2) SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR DESIGNING THE COMPENSATION NETWORK LOW NOISE OUTPUT DESIGN PCB LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE