Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices) - 6

ADSP-BF700/701/702/703/704/705/706/707
• A similar buffer that interrupts on fractional buffers (for
Trigger Routing Unit (TRU)
example, 1/2, 1/4). The TRU provides system-level sequence control without core • 1D DMA—uses a set of identical ping-pong buffers defined intervention. The TRU maps trigger masters (generators of trig- by a linked ring of two-word descriptor sets, each contain- gers) to trigger slaves (receivers of triggers). Slave endpoints can ing a link pointer and an address. be configured to respond to triggers in various ways. Common • 1D DMA—uses a linked list of 4 word descriptor sets con- applications enabled by the TRU include: taining a link pointer, an address, a length, and a • Automatically triggering the start of a DMA sequence after configuration. a sequence from another DMA channel completes • 2D DMA—uses an array of one-word descriptor sets, spec- • Software triggering ifying only the base DMA address. • Synchronization of concurrent activities • 2D DMA—uses a linked list of multi-word descriptor sets, specifying everything.
General-Purpose I/O (GPIO)
Each general-purpose port pin can be individually controlled by
Event Handling
manipulation of the port control, status, and interrupt registers: The processor provides event handling that supports both nest- • GPIO direction control register—Specifies the direction of ing and prioritization. Nesting allows multiple event service each individual GPIO pin as input or output. routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over ser- • GPIO control and status registers—A write one to modify vicing of a lower-priority event. The processor provides support mechanism allows any combination of individual GPIO for five different types of events: pins to be modified in a single instruction, without affect- ing the level of any other GPIO pins. • Emulation—An emulation event causes the processor to enter emulation mode, allowing command and control of • GPIO interrupt mask registers—Allow each individual the processor through the JTAG interface. GPIO pin to function as an interrupt to the processor. GPIO pins defined as inputs can be configured to generate • Reset—This event resets the processor. hardware interrupts, while output pins can be triggered by • Nonmaskable interrupt (NMI)—The NMI event can be software interrupts. generated either by the software watchdog timer, by the • GPIO interrupt sensitivity registers—Specify whether indi- NMI input signal to the processor, or by software. The vidual pins are level- or edge-sensitive and specify—if NMI event is frequently used as a power-down indicator to edge-sensitive—whether just the rising edge or both the ris- initiate an orderly shutdown of the system. ing and falling edges of the signal are significant. • Exceptions—Events that occur synchronously to program flow (in other words, the exception is taken before the
Pin Interrupts
instruction is allowed to complete). Conditions such as Every port pin on the processor can request interrupts in either data alignment violations and undefined instructions cause an edge-sensitive or a level-sensitive manner with programma- exceptions. ble polarity. Interrupt functionality is decoupled from GPIO • Interrupts —Events that occur asynchronously to program operation. Three system-level interrupt channels (PINT0–3) are flow. They are caused by input signals, timers, and other reserved for this purpose. Each of these interrupt channels can peripherals, as well as by an explicit software instruction. manage up to 32 interrupt pins. The assignment from pin to interrupt is not performed on a pin-by-pin basis. Rather, groups
System Event Controller (SEC)
of eight pins (half ports) can be flexibly assigned to interrupt The SEC manages the enabling, prioritization, and routing of channels. events from each system interrupt or fault source. Additionally, Every pin interrupt channel features a special set of 32-bit mem- it provides notification and identification of the highest priority ory-mapped registers that enable half-port assignment and active system interrupt request to the core and routes system interrupt management. This includes masking, identification, fault sources to its integrated fault management unit. The SEC and clearing of requests. These registers also enable access to the triggers core general-purpose interrupt IVG11. It is recom- respective pin states and use of the interrupt latches, regardless mended that IVG11 be set to allow self-nesting. The four lower of whether the interrupt is masked or not. Most control registers priority interrupts (IVG15-12) may be used for software feature multiple MMR address entries to write-one-to-set or interrupts. write-one-to-clear them individually.
Pin Multiplexing
The processor supports a flexible multiplexing scheme that mul- tiplexes the GPIO pins with various peripherals. A maximum of 4 peripherals plus GPIO functionality is shared by each GPIO pin. All GPIO pins have a bypass path feature—that is, when the Rev. D | Page 6 of 114 | February 2019 Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide