Datasheet ADSP-BF504 (Analog Devices) - 5

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ADSP-BF504
Blackfin processors support a modified Harvard architecture in The first block is the L1 instruction memory, consisting of combination with a hierarchical memory structure. Level 1 (L1) 32K bytes SRAM, of which 16K bytes can be configured as a memories are those that typically operate at the full processor four-way set-associative cache. This memory is accessed at full speed with little or no latency. At the L1 level, the instruction processor speed. memory holds instructions only. The data memory holds data, The second core-accessible memory block is the L1 data mem- and a dedicated scratchpad data memory stores stack and local ory, consisting of 32K bytes of SRAM, of which 16K bytes may variable information. be configured as cache. This memory block is accessed at full In addition, multiple L1 memory blocks are provided, offering a processor speed. configurable mix of SRAM and cache. The memory manage- The third memory block is 4K bytes of scratchpad SRAM, which ment unit (MMU) provides memory protection for individual runs at the same speed as the L1 memories, but this memory is tasks that may be operating on the core and can protect system only accessible as data SRAM and cannot be configured as cache registers from unintended access. memory. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has
0xFFFF FFFF
restricted access to certain system resources, thus providing a
CORE MEMORY MAPPED REGISTERS
protected software environment, while supervisor mode has
0xFFE0 0000 SYSTEM MEMORY MAPPED REGISTERS
unrestricted access to the system and core resources.
0xFFC0 0000 RESERVED
The Blackfin processor instruction set has been optimized so
0xFFB0 1000 INTERNAL SCRATCHPAD RAM (4K BYTES)
that 16-bit opcodes represent the most frequently used instruc-
0xFFB0 0000 RESERVED
tions, resulting in excellent compiled code density. Complex
0xFFA1 4000
DSP instructions are encoded into 32-bit opcodes, representing
RESERVED Y MAP 0xFFA0 8000
fully featured multifunction instructions. Blackfin processors
CCESSIBLE) L1 INSTRUCTION SRAM/CACHE (16K BYTES) 0xFFA0 4000 INTERNAL
support a limited multi-issue capability, where a 32-bit instruc-
MEMOR L1 INSTRUCTION BANK A SRAM (16K BYTES)
tion can be issued in parallel with two 16-bit instructions,
0xFFA0 0000 (CORE-A RESERVED
allowing the programmer to use many of the core resources in a
0xFF80 8000
single instruction cycle.
L1 DATA BANK A SRAM/CACHE (16K BYTES) 0xFF80 4000 L1 DATA BANK A SRAM (16K BYTES)
The Blackfin processor assembly language uses an algebraic syn-
0xFF80 0000
tax for ease of coding and readability. The architecture has been
RESERVED 0xEF00 1000
optimized for use in conjunction with the C/C++ compiler,
BOOT ROM (4K BYTES)
resulting in fast and efficient software implementations.
0xEF00 0000 RESERVED CCESSIBLE) Y MAP 0x2040 0000 MEMORY ARCHITECTURE RESERVED CE-A 0x2000 0000 EXTERNAL A MEMOR RESERVED
The Blackfin processor views memory as a single unified
0x0000 0000
4G byte address space, using 32-bit addresses. All resources,
(INTERF
including internal memory, external memory, and I/O control registers, occupy separate sections of this common address Figure 3. Internal/External Memory Map space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance
External (Interface-Accessible) Memory
balance of some very fast, low latency core-accessible memory External memory is accessed via the EBIU memory port. This as cache or SRAM and to provide larger, lower cost and perfor- 16-bit interface provides a glueless connection to the boot mance interface-accessible memory systems. See Figure 3. ROM. The core-accessible L1 memory system is the highest perfor-
I/O Memory Space
mance memory available to the Blackfin processor. The interface-accessible memory system, accessed through the The processor does not define a separate I/O space. All external bus interface unit (EBIU), provides access to the boot resources are mapped through the flat 32-bit address space. ROM. On-chip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of The memory DMA controller provides high bandwidth data the 4G byte address space. These are separated into two smaller movement capability. It can perform block transfers of code blocks. One contains the control MMRs for all core functions, or data between the internal memory and the external and the other contains the registers needed for setup and con- memory spaces. trol of the on-chip peripherals outside of the core. The MMRs
Internal (Core-Accessible) Memory
are accessible only in supervisor and emulation modes and appear as reserved space to on-chip peripherals. The processor has three blocks of core-accessible memory, providing high-bandwidth access to the core. Rev. C | Page 5 of 51 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory External (Interface-Accessible) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Up/Down Counters and Thumbwheel Interfaces 3-Phase PWM Units Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions RSI Interface Controller Area Network (CAN) Interface TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF504 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) ACM Interface Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF504 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Processor—Absolute Maximum Ratings ESD Sensitivity Processor—Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing JTAG Test And Emulation Port Timing Processor—Output Drive Currents Processor—Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Processor—Environmental Conditions 88-Lead LFCSP Lead Assignment Outline Dimensions Ordering Guide