Datasheet A17700 (Allegro) - 10

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Pressure Sensor Interface and Signal Conditioning IC A17700 with Polynomial Signal Compensation and Advanced Diagnostics FUNCTIONAL DESCRIPTION
The A17700 is a signal conditioning IC that accepts a differential
Output Response Time
Wheatstone bridge input. The bridge signal is amplified with a programmable gain amplifier, and a coarse offset is applied. The The output response time is the time interval between a) when purpose of this front end is to fill the ADC range as much as pos- input stimulus reaches 80% of its final value and b) the sensor sible, but also ensure that the ADC is not saturated over tempera- reaches 80% of its final output, input signal being a step impulse ture and operating conditions. The DSP logic will then provide (square signal). a filter to reduce noise (also setting the effective operating (%) Input Stimulus (Pressure) bandwidth of the device) to the application bandwidth and apply fine signal adjustments and temperature compensation through 80 Device Output polynomial equation (up to poly4,4). The output can be selected between ratiometric analog output, SENT, or PWM. Response Time, tresp
Bandwidth Selection
t The internal filter bandwidth can be adjusted to minimize output
Figure 4: Output Response Time Definition
noise and improve resolution in function of the system band- width. The choice of bandwidth will be a compromise between response time and system resolution. Table 1 is provided to help
Power-On Time
define better option for the system. Power-On Time is defined as the time it takes for the output to settle within ±10% of its steady-state value under an applied
Table 1: Bandwidth Selection Table
stimulus (pressure), after the power supply has reached its mini-
Ideal Noise-Free
mum specified operating voltage, VCC(min).
Bandwidth Typical Resolution at Given Code Bandwidth Response
V
Time Bandwidth (2.2 kΩ bridge and 25 mV/V sensitivity)
VCC VCC(typ.) 0 (Default) 2.5 kHz 250 µs 13.7 bits VOUT 90% VOUT 1 0.3 kHz 1350 µs 15.0 bits 2 0.6 kHz 750 µs 14.6 bits 3 1.0 kHz 470 µs 14.4 bits VCC(min.) t 4 2.5 kHz 250 µs 13.7 bits PO t1 t2 5 5.0 kHz 170 µs 12.7 bits t1= time at which power supply reaches 6 10 kHz 130 µs 11.8 bits minimum specified operating voltage 7 20 kHz 110 µs 10.6 bits t2= time at which output voltage settles within ±10% of its steady state value 0 t
Figure 5: Power-On Time Definition
10 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Functional Block Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Pinout Diagram and Terminal List Operating Characteristics Functional Description Bandwidth Selection Output Response Time Power-On Time Front End Gain Adjustment Front End Differential Offset Adjustment Input Signal Range Calculation Fine Adjustment and Temperature Compensation Output Protocols Digital Output Mode Selection Digital Output Driver Fall Time Selection Broken Wire Detection Diagnostic Features Programming: Manchester Communication Entering Manchester Coding Manchester Interface Message Structure CRC Device Access Shadow Registers Device EEPROM and Register Access Lock EEPROM Map Volatile Registers Map Power Derating Package Outline Drawing