Datasheet MBRD835L, SBRD8835L (ON Semiconductor) - 5
| 制造商 | ON Semiconductor |
| 描述 | Schottky Barrier Rectifier, 35 V, 8.0 A |
| 页数 / 页 | 7 / 5 — PACKAGE DIMENSIONS. DPAK (SINGLE GAUGE). SCALE 1:1. DETAIL A. INCHES. … |
| 修订版 | 13 |
| 文件格式/大小 | PDF / 180 Kb |
| 文件语言 | 英语 |
PACKAGE DIMENSIONS. DPAK (SINGLE GAUGE). SCALE 1:1. DETAIL A. INCHES. MILLIMETERS. NOTE 7. DIM. MIN. MAX. BOTTOM VIEW. SIDE VIEW. TOP VIEW. GAUGE
该数据表的模型线
文件文字版本
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
4
DPAK (SINGLE GAUGE)
CASE 369C ISSUE F 1 2 DATE 21 JUL 2015 3
SCALE 1:1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME
A
Y14.5M, 1994.
E C
2. CONTROLLING DIMENSION: INCHES.
A
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
b3
MENSIONS b3, L3 and Z.
B c2
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL
4
NOT EXCEED 0.006 INCHES PER SIDE.
L3 Z
5. DIMENSIONS D AND E ARE DETERMINED AT THE
D
OUTERMOST EXTREMES OF THE PLASTIC BODY.
DETAIL A H
6. DATUMS A AND B ARE DETERMINED AT DATUM
1 2 3
PLANE H. 7. OPTIONAL MOLD FEATURE.
L4 INCHES MILLIMETERS NOTE 7 b2 c DIM MIN MAX MIN MAX BOTTOM VIEW A
0.086 0.094 2.18 2.38
e A1
0.000 0.005 0.00 0.13
SIDE VIEW b b
0.025 0.035 0.63 0.89 0.005 (0.13) M C
b2
0.028 0.045 0.72 1.14
TOP VIEW b3
0.180 0.215 4.57 5.46
c
0.018 0.024 0.46 0.61
c2
0.018 0.024 0.46 0.61
Z Z D
0.235 0.245 5.97 6.22
H E
0.250 0.265 6.35 6.73
e
0.090 BSC 2.29 BSC
GAUGE SEATING L2 H
0.370 0.410 9.40 10.41
PLANE C PLANE L
0.055 0.070 1.40 1.78
L1
0.114 REF 2.90 REF
L2
0.020 BSC 0.51 BSC
L L3
0.035 0.050 0.89 1.27
A1 BOTTOM VIEW L4
−−− 0.040 −−− 1.01
L1 ALTERNATE Z
0.155 −−− 3.93 −−−
CONSTRUCTIONS DETAIL A ROTATED 90 CW
5
GENERIC MARKING DIAGRAM*
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE PIN 1. GATE 2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE 2. ANODE 3. EMITTER 3. SOURCE 3. ANODE 3. GATE 3. CATHODE 4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE 4. ANODE XXXXXXG AYWW ALYWW XXX STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10: XXXXXG PIN 1. MT1 PIN 1. GATE PIN 1. N/C PIN 1. ANODE PIN 1. CATHODE 2. MT2 2. COLLECTOR 2. CATHODE 2. CATHODE 2. ANODE 3. GATE 3. EMITTER 3. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. MT2 4. COLLECTOR 4. CATHODE 4. CATHODE 4. ANODE
IC Discrete SOLDERING FOOTPRINT*
XXXXXX = Device Code A = Assembly Location 6.20 3.00 L = Wafer Lot 0.244 0.118 Y = Year 2.58 WW = Work Week 0.102 G = Pb−Free Package 5.80 *This information is generic. Please refer 1.60 6.17 to device data sheet for actual part 0.228 0.063 0.243 marking. SCALE 3:1 ǒ mm Ǔ inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER: 98AON10527D
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed
STATUS: ON SEMICONDUCTOR STANDARD
versions are uncontrolled except when stamped
NEW STANDARD:
“CONTROLLED COPY” in red.
REF TO JEDEC TO−252
© Semiconductor Components Industries, LLC, 2002
http://onsemi.com
Case Outline Number:
October, 2002 − Rev. 0 DESCRIPTION: DPAK SINGLE GAUGE SURF 1 ACE MOUNT PAGE XXX 1 OF 2
PACKAGE DIMENSIONS
4
DPAK (SINGLE GAUGE)
CASE 369C ISSUE F 1 2 DATE 21 JUL 2015 3
SCALE 1:1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME
A
Y14.5M, 1994.
E C
2. CONTROLLING DIMENSION: INCHES.
A
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
b3
MENSIONS b3, L3 and Z.
B c2
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL
4
NOT EXCEED 0.006 INCHES PER SIDE.
L3 Z
5. DIMENSIONS D AND E ARE DETERMINED AT THE
D
OUTERMOST EXTREMES OF THE PLASTIC BODY.
DETAIL A H
6. DATUMS A AND B ARE DETERMINED AT DATUM
1 2 3
PLANE H. 7. OPTIONAL MOLD FEATURE.
L4 INCHES MILLIMETERS NOTE 7 b2 c DIM MIN MAX MIN MAX BOTTOM VIEW A
0.086 0.094 2.18 2.38
e A1
0.000 0.005 0.00 0.13
SIDE VIEW b b
0.025 0.035 0.63 0.89 0.005 (0.13) M C
b2
0.028 0.045 0.72 1.14
TOP VIEW b3
0.180 0.215 4.57 5.46
c
0.018 0.024 0.46 0.61
c2
0.018 0.024 0.46 0.61
Z Z D
0.235 0.245 5.97 6.22
H E
0.250 0.265 6.35 6.73
e
0.090 BSC 2.29 BSC
GAUGE SEATING L2 H
0.370 0.410 9.40 10.41
PLANE C PLANE L
0.055 0.070 1.40 1.78
L1
0.114 REF 2.90 REF
L2
0.020 BSC 0.51 BSC
L L3
0.035 0.050 0.89 1.27
A1 BOTTOM VIEW L4
−−− 0.040 −−− 1.01
L1 ALTERNATE Z
0.155 −−− 3.93 −−−
CONSTRUCTIONS DETAIL A ROTATED 90 CW
5
GENERIC MARKING DIAGRAM*
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE PIN 1. GATE 2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE 2. ANODE 3. EMITTER 3. SOURCE 3. ANODE 3. GATE 3. CATHODE 4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE 4. ANODE XXXXXXG AYWW ALYWW XXX STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10: XXXXXG PIN 1. MT1 PIN 1. GATE PIN 1. N/C PIN 1. ANODE PIN 1. CATHODE 2. MT2 2. COLLECTOR 2. CATHODE 2. CATHODE 2. ANODE 3. GATE 3. EMITTER 3. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. MT2 4. COLLECTOR 4. CATHODE 4. CATHODE 4. ANODE
IC Discrete SOLDERING FOOTPRINT*
XXXXXX = Device Code A = Assembly Location 6.20 3.00 L = Wafer Lot 0.244 0.118 Y = Year 2.58 WW = Work Week 0.102 G = Pb−Free Package 5.80 *This information is generic. Please refer 1.60 6.17 to device data sheet for actual part 0.228 0.063 0.243 marking. SCALE 3:1 ǒ mm Ǔ inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER: 98AON10527D
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed
STATUS: ON SEMICONDUCTOR STANDARD
versions are uncontrolled except when stamped
NEW STANDARD:
“CONTROLLED COPY” in red.
REF TO JEDEC TO−252
© Semiconductor Components Industries, LLC, 2002
http://onsemi.com
Case Outline Number:
October, 2002 − Rev. 0 DESCRIPTION: DPAK SINGLE GAUGE SURF 1 ACE MOUNT PAGE XXX 1 OF 2