Datasheet STK14CA8C (Infineon)
| 制造商 | Infineon |
| 描述 | 1-Mbit (128K × 8) nvSRAM |
| 页数 / 页 | 21 / 1 — STK14CA8C. 1-Mbit (128K × 8) nvSRAM. Features. Functional Description. … |
| 文件格式/大小 | PDF / 441 Kb |
| 文件语言 | 英语 |
STK14CA8C. 1-Mbit (128K × 8) nvSRAM. Features. Functional Description. Logic Block Diagram. Cypress Semiconductor Corporation
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STK14CA8C
1-Mbit (128K × 8) nvSRAM
1-Mbit (128K × 8) nvSRAM Features Functional Description
■ 35 ns access time The Cypress STK14CA8C is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as ■ Internally organized as 128K × 8 128KB. The embedded nonvolatile elements incorporate ■ Hands-off automatic STORE on power-down with only a smal QuantumTrap technology, producing the world’s most reliable capacitor nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly ■ STORE to QuantumTrap nonvolatile elements initiated by reliable QuantumTrap cell. Data transfers from the SRAM to the software, device pin, or autostore on power-down nonvolatile elements (the STORE operation) takes place ■ RECALL to SRAM initiated by software or power-up automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. ■ Infinite read, write, and RECALL cycles Both the STORE and RECALL operations are also available ■ 1 million STORE cycles to QuantumTrap under software control. ■ 20-year data retention ■ Single 5 V + 10% operation ■ Industrial and Military temperatures ■ 32-pin CDIP package
Logic Block Diagram
VCC VCAP Quatrum Trap 1024 X 1024 A5 R O POWER CONTROL A6 STORE W A7 RECALL A8 D A9 STORE/RECALL E HSB A STATIC RAM CONTROL 12 C A ARRAY 13 O 1024 X 1024 A14 D A15 E SOFTWARE A14 - A2 A R DETECT 16 DQ0 I DQ1 N P DQ2 U DQ3 T B DQ4 U DQ5 F F DQ6 COLUMN I/O E DQ7 R S COLUMN DEC OE A0 A1 A2 A3 A4 A10 A11 CE WE
Cypress Semiconductor Corporation
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-23970 Rev. *A Revised March 26, 2019 Document Outline 1-Mbit (128K × 8) nvSRAM Features Functional Description Logic Block Diagram Contents Pinout Pin Definitions Device Operation SRAM Read SRAM Write AutoStore Operation Hardware STORE Operation Hardware RECALL (Power-up) Software STORE Software RECALL Preventing AutoStore Data Protection Maximum Ratings Operating Range DC Electrical Characteristics Data Retention and Endurance Capacitance Thermal Resistance AC Test Loads AC Test Conditions AC Switching Characteristics SRAM Read Cycle SRAM Write Cycle Switching Waveforms AutoStore/Power-up RECALL Switching Waveforms Software Controlled STORE/RECALL Cycle Switching Waveforms Hardware STORE Cycle Switching Waveforms Truth Table For SRAM Operations Ordering Information Ordering Code Definitions for Industrial Temperature Ordering Code Definitions for Military Temperature Package Diagram Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
1-Mbit (128K × 8) nvSRAM
1-Mbit (128K × 8) nvSRAM Features Functional Description
■ 35 ns access time The Cypress STK14CA8C is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as ■ Internally organized as 128K × 8 128KB. The embedded nonvolatile elements incorporate ■ Hands-off automatic STORE on power-down with only a smal QuantumTrap technology, producing the world’s most reliable capacitor nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly ■ STORE to QuantumTrap nonvolatile elements initiated by reliable QuantumTrap cell. Data transfers from the SRAM to the software, device pin, or autostore on power-down nonvolatile elements (the STORE operation) takes place ■ RECALL to SRAM initiated by software or power-up automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. ■ Infinite read, write, and RECALL cycles Both the STORE and RECALL operations are also available ■ 1 million STORE cycles to QuantumTrap under software control. ■ 20-year data retention ■ Single 5 V + 10% operation ■ Industrial and Military temperatures ■ 32-pin CDIP package
Logic Block Diagram
VCC VCAP Quatrum Trap 1024 X 1024 A5 R O POWER CONTROL A6 STORE W A7 RECALL A8 D A9 STORE/RECALL E HSB A STATIC RAM CONTROL 12 C A ARRAY 13 O 1024 X 1024 A14 D A15 E SOFTWARE A14 - A2 A R DETECT 16 DQ0 I DQ1 N P DQ2 U DQ3 T B DQ4 U DQ5 F F DQ6 COLUMN I/O E DQ7 R S COLUMN DEC OE A0 A1 A2 A3 A4 A10 A11 CE WE
Cypress Semiconductor Corporation
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-23970 Rev. *A Revised March 26, 2019 Document Outline 1-Mbit (128K × 8) nvSRAM Features Functional Description Logic Block Diagram Contents Pinout Pin Definitions Device Operation SRAM Read SRAM Write AutoStore Operation Hardware STORE Operation Hardware RECALL (Power-up) Software STORE Software RECALL Preventing AutoStore Data Protection Maximum Ratings Operating Range DC Electrical Characteristics Data Retention and Endurance Capacitance Thermal Resistance AC Test Loads AC Test Conditions AC Switching Characteristics SRAM Read Cycle SRAM Write Cycle Switching Waveforms AutoStore/Power-up RECALL Switching Waveforms Software Controlled STORE/RECALL Cycle Switching Waveforms Hardware STORE Cycle Switching Waveforms Truth Table For SRAM Operations Ordering Information Ordering Code Definitions for Industrial Temperature Ordering Code Definitions for Military Temperature Package Diagram Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support