Datasheet MM5600 (Menlo Micro) - 6
| 制造商 | Menlo Micro |
| 描述 | 40Gbps DPDT Differential Switchwith Integrated Driver |
| 页数 / 页 | 17 / 6 — PRELIMINARY DATASHEET v1.1. Table 3. Parameter. Minimum. Typical. … |
| 文件格式/大小 | PDF / 753 Kb |
| 文件语言 | 英语 |
PRELIMINARY DATASHEET v1.1. Table 3. Parameter. Minimum. Typical. Maximum. Unit. Clock Frequency fCLK. Clock Width High and Low tWL,tWH
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6 MM5600 - 40 Gbps DPDT Differential Switch
PRELIMINARY DATASHEET v1.1 Table 3
Driver Interface AC Electrical Specifications
Parameter Minimum Typical Maximum Unit Clock Frequency fCLK
0 8 MHz
Clock Width High and Low tWL,tWH
62 ns
Data Setup Time before Clock Rises tSU
15 ns
Data Hold Time after Clock Rises tH
30 ns
Latch Enable Pulse Width tWLE
80 ns
Latch Enable Delay Time after Rising Edge
35 ns
of Clock tDLE Latch Enable Setup Time before Clock Rises
40 ns
tSLE Delay Time Clock to Data Low to High tDLH
110 ns
Delay Time Clock to Data High to Low tDHL
110 ns
All Logic Inputs tr, tf
5 ns Figure 1: Driver Interface Timing Diagram © 2021 Menlo Microsystems, Inc. | All Rights Reserved | www.menlomicro.com
PRELIMINARY DATASHEET v1.1 Table 3
Driver Interface AC Electrical Specifications
Parameter Minimum Typical Maximum Unit Clock Frequency fCLK
0 8 MHz
Clock Width High and Low tWL,tWH
62 ns
Data Setup Time before Clock Rises tSU
15 ns
Data Hold Time after Clock Rises tH
30 ns
Latch Enable Pulse Width tWLE
80 ns
Latch Enable Delay Time after Rising Edge
35 ns
of Clock tDLE Latch Enable Setup Time before Clock Rises
40 ns
tSLE Delay Time Clock to Data Low to High tDLH
110 ns
Delay Time Clock to Data High to Low tDHL
110 ns
All Logic Inputs tr, tf
5 ns Figure 1: Driver Interface Timing Diagram © 2021 Menlo Microsystems, Inc. | All Rights Reserved | www.menlomicro.com