Datasheet PMN50XP (NXP) - 5
| 制造商 | NXP |
| 描述 | P-channel TrenchMOS extremely low level FET |
| 页数 / 页 | 11 / 5 — NXP Semiconductors. PMN50XP. P-channel TrenchMOS extremely low level FET. … |
| 文件格式/大小 | PDF / 153 Kb |
| 文件语言 | 英语 |
NXP Semiconductors. PMN50XP. P-channel TrenchMOS extremely low level FET. Table 6. Characteristics. Symbol. Parameter. Conditions. Min
该数据表的模型线
文件文字版本
link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7
NXP Semiconductors PMN50XP P-channel TrenchMOS extremely low level FET Table 6. Characteristics
…continued
Symbol Parameter Conditions Min Typ Max Unit
I ≤ GSS gate leakage current VGS 12 V; VDS = 0 V; Tj = 25 °C - -10 -100 nA V ≥ GS 12 V; VDS = 0 V; Tj = 25 °C - -10 -100 nA RDSon drain-source on-state VGS = -4.5 V; ID = -2.8 A; - 48 60 mΩ resistance Tj = 25 °C; see Figure 7 and 8 VGS = -4.5 V; ID = -2.8 A; - 77 96 mΩ Tj = 150 °C; see Figure 7 and 8 VGS = -2.5 V; ID = -2.3 A; - 65 80 mΩ Tj = 25 °C; see Figure 7 and 8
Dynamic characteristics
QG(tot) total gate charge ID = -4.7 A; VDS = -10 V; - 10 - nC VGS = -4.5 V; Tj = 25 °C; see Figure 9 and 10 QGS gate-source charge ID = -4.7 A; VDS = -10 V; - 2.2 - nC VGS = -4.5 V; Tj = 25 °C; see Figure 9 and 10 QGD gate-drain charge ID = -4.7 A; VDS = -10 V; - 1.3 - nC VGS = -4.5 V; Tj = 25 °C; see Figure 9 and 10 Ciss input capacitance VDS = -20 V; VGS = 0 V; - 1020 - pF f = 1 MHz; Tj = 25 °C; see Figure 11 Coss output capacitance VGS = 0 V; VDS = -20 V; - 140 - pF f = 1 MHz; Tj = 25 °C; see Figure 11 Crss reverse transfer VDS = -20 V; VGS = 0 V; - 100 - pF capacitance f = 1 MHz; Tj = 25 °C; see Figure 11 td(on) turn-on delay time RG(ext) = 6 Ω; RL = 10 Ω; - 8.5 - ns VDS = -10 V; VGS = -4.5 V; Tj = 25 °C tr rise time RG(ext) = 6 Ω; RL = 10 Ω; - 7.5 - ns VDS = -10 V; VGS = -4.5 V; Tj = 25 °C td(off) turn-off delay time VDS = -10 V; RL = 10 Ω; - 82 - ns VGS = -4.5 V; RG(ext) = 6 Ω; Tj = 25 °C tf fall time RG(ext) = 6 Ω; RL = 6 Ω; - 35 - ns VDS = -10 V; VGS = -4.5 V; Tj = 25 °C VGS(pl) gate-source plateau VDS = -10 V; ID = -4.7 A; - -1.6 - V voltage Tj = 25 °C; see Figure 9 and 10
Source-drain diode
VSD source-drain voltage IS = -1.7 A; VGS = 0 V; Tj = 25 °C - -0.77 -1.2 V trr reverse recovery time IS = 3.5 A; dIS/dt = -100 A/μs; - - - ns VGS = 0 V; VDS = 20 V; Tj = 25 °C PMN50XP_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 October 2007 5 of 11
Document Outline 1. Product profile 1.1 General description 1.2 Features 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 6. Characteristics 7. Package outline 8. Revision history 9. Legal information 9.1 Data sheet status 9.2 Definitions 9.3 Disclaimers 9.4 Trademarks 10. Contact information 11. Contents
NXP Semiconductors PMN50XP P-channel TrenchMOS extremely low level FET Table 6. Characteristics
…continued
Symbol Parameter Conditions Min Typ Max Unit
I ≤ GSS gate leakage current VGS 12 V; VDS = 0 V; Tj = 25 °C - -10 -100 nA V ≥ GS 12 V; VDS = 0 V; Tj = 25 °C - -10 -100 nA RDSon drain-source on-state VGS = -4.5 V; ID = -2.8 A; - 48 60 mΩ resistance Tj = 25 °C; see Figure 7 and 8 VGS = -4.5 V; ID = -2.8 A; - 77 96 mΩ Tj = 150 °C; see Figure 7 and 8 VGS = -2.5 V; ID = -2.3 A; - 65 80 mΩ Tj = 25 °C; see Figure 7 and 8
Dynamic characteristics
QG(tot) total gate charge ID = -4.7 A; VDS = -10 V; - 10 - nC VGS = -4.5 V; Tj = 25 °C; see Figure 9 and 10 QGS gate-source charge ID = -4.7 A; VDS = -10 V; - 2.2 - nC VGS = -4.5 V; Tj = 25 °C; see Figure 9 and 10 QGD gate-drain charge ID = -4.7 A; VDS = -10 V; - 1.3 - nC VGS = -4.5 V; Tj = 25 °C; see Figure 9 and 10 Ciss input capacitance VDS = -20 V; VGS = 0 V; - 1020 - pF f = 1 MHz; Tj = 25 °C; see Figure 11 Coss output capacitance VGS = 0 V; VDS = -20 V; - 140 - pF f = 1 MHz; Tj = 25 °C; see Figure 11 Crss reverse transfer VDS = -20 V; VGS = 0 V; - 100 - pF capacitance f = 1 MHz; Tj = 25 °C; see Figure 11 td(on) turn-on delay time RG(ext) = 6 Ω; RL = 10 Ω; - 8.5 - ns VDS = -10 V; VGS = -4.5 V; Tj = 25 °C tr rise time RG(ext) = 6 Ω; RL = 10 Ω; - 7.5 - ns VDS = -10 V; VGS = -4.5 V; Tj = 25 °C td(off) turn-off delay time VDS = -10 V; RL = 10 Ω; - 82 - ns VGS = -4.5 V; RG(ext) = 6 Ω; Tj = 25 °C tf fall time RG(ext) = 6 Ω; RL = 6 Ω; - 35 - ns VDS = -10 V; VGS = -4.5 V; Tj = 25 °C VGS(pl) gate-source plateau VDS = -10 V; ID = -4.7 A; - -1.6 - V voltage Tj = 25 °C; see Figure 9 and 10
Source-drain diode
VSD source-drain voltage IS = -1.7 A; VGS = 0 V; Tj = 25 °C - -0.77 -1.2 V trr reverse recovery time IS = 3.5 A; dIS/dt = -100 A/μs; - - - ns VGS = 0 V; VDS = 20 V; Tj = 25 °C PMN50XP_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 October 2007 5 of 11
Document Outline 1. Product profile 1.1 General description 1.2 Features 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 6. Characteristics 7. Package outline 8. Revision history 9. Legal information 9.1 Data sheet status 9.2 Definitions 9.3 Disclaimers 9.4 Trademarks 10. Contact information 11. Contents